library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
    signal fpuDone : std_logic;
	signal START : std_logic;
    type AddState is (
        ADD_IDLE,
        ADD_SET_SIGNALS,
		ADD_RUNNING,
        ADD_DONE
    );
	signal current_add_state : AddState;
	signal next_add_state : AddState;

begin
    f1:ENTITY work.float_add PORT MAP(CLK => CLK, RESET => RESET, START => START, A => signal_a_readdata, B => signal_b_readdata, done => fpuDone, sum => signal_writedata);
    
    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
            when work.task.TASK_RUNNING =>
				if(current_add_state = ADD_DONE) then
		   			index <= index + 1;
				end if;
            when work.task.TASK_DONE =>
                index <= 0;
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

	add_state_transitions : process ( current_add_state, fpuDone, current_task_state)
	begin
		next_add_state <= current_add_state;
		case current_add_state is
		when ADD_IDLE =>
			if(current_task_state = work.task.TASK_RUNNING) then
				next_add_state <= ADD_SET_SIGNALS;
			end if;
		when ADD_SET_SIGNALS =>
			next_add_state <= ADD_RUNNING;
		when ADD_RUNNING =>
			if(fpuDone = '1') then
				next_add_state <= ADD_DONE;
			end if;
		when ADD_DONE =>
			next_add_state <= ADD_IDLE;
		end case;
	end process add_state_transitions;

    add : process (clk, reset) is
	begin
		if ( reset = '1' ) then
			current_add_state <= ADD_IDLE;
		elsif ( rising_edge( clk ) ) then
			current_add_state <= next_add_state;
			case next_add_state is
			when ADD_IDLE =>
				START <= '0';
				signal_write <= '0';
			when ADD_SET_SIGNALS =>
				signal_a_read <= '1';
				signal_b_read <= '1';
			when ADD_RUNNING =>
				signal_a_read <= '0';
				signal_b_read <= '0';
				START <= '1';
			when ADD_DONE =>
				START <= '0';
				signal_write <= '1';
			end case;
		end if;
	end process add;
end architecture rtl;
