signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

--Initialisierung der weiteren Ablaufstruktur
type AddState is (
	AddIdle,
	AddWait1,
	AddStart,	
	AddAddition,
	AddStore 
);

--Signale fuer die Zustandsmaschine
signal current_add_state : AddState;
signal next_add_state : AddState;
signal A      : std_logic_vector(31 downto 0);
signal B      : std_logic_vector(31 downto 0);
signal start  : std_logic;
signal done   : std_logic;
signal sum    : std_logic_vector ( 31 downto 0 );


begin


    c_float_add : entity work.float_add
	PORT MAP (
	  	A      => A,
	       	B      => B,
	       	clk    => clk,
	       	reset  => reset,
	       	start  => start,
	       	done   => done,
	       	sum    => sum
	       	);


    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

----------------------------------------------------------------------
	add_state_transitions : process ( all ) is
	begin
		next_add_state <= current_add_state;
		case current_add_state is
			when AddIdle =>
				if ( current_task_state = work.task.TASK_RUNNING ) then -- Weiterschaltbedingung					
					next_add_state <= AddStart;	
				end if;

			when AddStart =>
				next_add_state <= AddAddition;

			when AddAddition =>
				next_add_state <= AddWait1;	-- Weiterschaltbedingung

			when AddWait1 =>
				if ( done = '1' ) then	-- Weiterschaltbedingung
					next_add_state <= AddStore;
				end if;

			when AddStore =>
				next_add_state <= AddIdle; 	-- Weiterschaltbedingung

		end case;
	end process add_state_transitions;
----------------------------------------------------------------------
    sync : process ( clk, reset ) is
    begin							--INDEX WIRD NOCH JEDEN TAKT HOCHGEZÄHLT UND NICHT NUR WENN DAS ERGEBNIS GESPEICHERT WIRD
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
	    current_add_state <= AddIdle;
            index <= 0;
	    start <= '0';
	    A <= ( others => '0' );
	    B <= ( others => '0' );
	    
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
                signal_write <= '0';
            when work.task.TASK_RUNNING =>
                --index <= index + 1;
                signal_write <= '1';
                signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                index <= 0;
                signal_write <= '0';
            end case;

		-------------------------------------------
	    current_add_state <= next_add_state;
	    signal_write <= '0';
	    signal_a_read <= '0';
	    signal_b_read <= '0';
	    case next_add_state is
		when AddIdle =>
			signal_write <= '0';
			start <= '0';
		when AddStart =>
			--start <= '1';
			
		when AddAddition =>
			start <= '1';
			signal_a_read <= '1';
			signal_b_read <= '1';
			A <= signal_a_readdata;
			B <= signal_b_readdata;			

		when AddWait1 =>
			signal_a_read <= '0';
			signal_b_read <= '0';

		when AddStore =>
			signal_write <= '1';
			signal_writedata <= sum;
			index <= index + 1;


	   end case;
		-------------------------------------------
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;