77 lines
2.2 KiB
VHDL
77 lines
2.2 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity crc is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity crc;
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architecture rtl of crc is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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