278 lines
10 KiB
Coq
278 lines
10 KiB
Coq
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//----------------------------------------------------------------------
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// SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT
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//----------------------------------------------------------------------
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module SdfUnit #(
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parameter N = 64, // Number of FFT Point
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parameter M = 64, // Twiddle Resolution
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parameter WIDTH = 16 // Data Bit Length
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)(
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input clock, // Master Clock
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input reset, // Active High Asynchronous Reset
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input di_en, // Input Data Enable
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input [WIDTH-1:0] di_re, // Input Data (Real)
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input [WIDTH-1:0] di_im, // Input Data (Imag)
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output do_en, // Output Data Enable
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output [WIDTH-1:0] do_re, // Output Data (Real)
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output [WIDTH-1:0] do_im // Output Data (Imag)
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);
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// log2 constant function
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function integer log2;
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input integer x;
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integer value;
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begin
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value = x-1;
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for (log2=0; value>0; log2=log2+1)
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value = value>>1;
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end
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endfunction
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localparam LOG_N = log2(N); // Bit Length of N
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localparam LOG_M = log2(M); // Bit Length of M
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//----------------------------------------------------------------------
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// Internal Regs and Nets
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//----------------------------------------------------------------------
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// 1st Butterfly
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reg [LOG_N-1:0] di_count; // Input Data Count
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wire bf1_bf; // Butterfly Add/Sub Enable
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wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real)
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wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag)
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wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real)
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wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag)
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wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real)
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wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag)
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wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real)
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wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag)
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wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real)
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wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag)
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wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real)
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wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag)
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wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real)
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wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag)
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reg bf1_sp_en; // Single-Path Data Enable
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reg [LOG_N-1:0] bf1_count; // Single-Path Data Count
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wire bf1_start; // Single-Path Output Trigger
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wire bf1_end; // End of Single-Path Data
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wire bf1_mj; // Twiddle (-j) Enable
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reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real)
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reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag)
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// 2nd Butterfly
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reg bf2_bf; // Butterfly Add/Sub Enable
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wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real)
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wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag)
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wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real)
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wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag)
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wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real)
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wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag)
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wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real)
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wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag)
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wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real)
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wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag)
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wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real)
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wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag)
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wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real)
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wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag)
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reg bf2_sp_en; // Single-Path Data Enable
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reg [LOG_N-1:0] bf2_count; // Single-Path Data Count
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reg bf2_start; // Single-Path Output Trigger
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wire bf2_end; // End of Single-Path Data
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reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real)
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reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag)
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reg bf2_do_en; // 2nd Butterfly Output Data Enable
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// Multiplication
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wire[1:0] tw_sel; // Twiddle Select (2n/n/3n)
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wire[LOG_N-3:0] tw_num; // Twiddle Number (n)
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wire[LOG_N-1:0] tw_addr; // Twiddle Table Address
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wire[WIDTH-1:0] tw_re; // Twiddle Factor (Real)
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wire[WIDTH-1:0] tw_im; // Twiddle Factor (Imag)
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reg mu_en; // Multiplication Enable
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wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real)
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wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag)
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wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real)
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wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag)
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reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real)
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reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag)
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reg mu_do_en; // Multiplication Output Data Enable
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//----------------------------------------------------------------------
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// 1st Butterfly
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//----------------------------------------------------------------------
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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di_count <= {LOG_N{1'b0}};
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end else begin
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di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
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end
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end
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assign bf1_bf = di_count[LOG_M-1];
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// Set unknown value x for verification
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assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
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assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
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assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
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assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
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Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
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.x0_re (bf1_x0_re ), // i
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.x0_im (bf1_x0_im ), // i
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.x1_re (bf1_x1_re ), // i
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.x1_im (bf1_x1_im ), // i
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.y0_re (bf1_y0_re ), // o
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.y0_im (bf1_y0_im ), // o
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.y1_re (bf1_y1_re ), // o
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.y1_im (bf1_y1_im ) // o
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);
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DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
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.clock (clock ), // i
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.di_re (db1_di_re ), // i
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.di_im (db1_di_im ), // i
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.do_re (db1_do_re ), // o
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.do_im (db1_do_im ) // o
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);
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assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
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assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
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assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
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assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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bf1_sp_en <= 1'b0;
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bf1_count <= {LOG_N{1'b0}};
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end else begin
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bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
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bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
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end
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end
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assign bf1_start = (di_count == (2**(LOG_M-1)-1));
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assign bf1_end = (bf1_count == (2**LOG_N-1));
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assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
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always @(posedge clock) begin
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bf1_do_re <= bf1_sp_re;
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bf1_do_im <= bf1_sp_im;
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end
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//----------------------------------------------------------------------
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// 2nd Butterfly
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//----------------------------------------------------------------------
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always @(posedge clock) begin
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bf2_bf <= bf1_count[LOG_M-2];
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end
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// Set unknown value x for verification
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assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
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assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
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assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
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assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
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// Negative bias occurs when RH=0 and positive bias occurs when RH=1.
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// Using both alternately reduces the overall rounding error.
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Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
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.x0_re (bf2_x0_re ), // i
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.x0_im (bf2_x0_im ), // i
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.x1_re (bf2_x1_re ), // i
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.x1_im (bf2_x1_im ), // i
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.y0_re (bf2_y0_re ), // o
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.y0_im (bf2_y0_im ), // o
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.y1_re (bf2_y1_re ), // o
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.y1_im (bf2_y1_im ) // o
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);
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DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
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.clock (clock ), // i
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.di_re (db2_di_re ), // i
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.di_im (db2_di_im ), // i
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.do_re (db2_do_re ), // o
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.do_im (db2_do_im ) // o
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);
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assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
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assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
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assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
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assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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bf2_sp_en <= 1'b0;
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bf2_count <= {LOG_N{1'b0}};
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end else begin
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bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
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bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
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end
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end
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always @(posedge clock) begin
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bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
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end
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assign bf2_end = (bf2_count == (2**LOG_N-1));
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always @(posedge clock) begin
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bf2_do_re <= bf2_sp_re;
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bf2_do_im <= bf2_sp_im;
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end
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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bf2_do_en <= 1'b0;
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end else begin
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bf2_do_en <= bf2_sp_en;
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end
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end
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//----------------------------------------------------------------------
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// Multiplication
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//----------------------------------------------------------------------
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assign tw_sel[1] = bf2_count[LOG_M-2];
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assign tw_sel[0] = bf2_count[LOG_M-1];
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assign tw_num = bf2_count << (LOG_N-LOG_M);
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assign tw_addr = tw_num * tw_sel;
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Twiddle TW (
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.clock (clock ), // i
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.addr (tw_addr), // i
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.tw_re (tw_re ), // o
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.tw_im (tw_im ) // o
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);
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// Multiplication is bypassed when twiddle address is 0.
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always @(posedge clock) begin
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mu_en <= (tw_addr != {LOG_N{1'b0}});
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end
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// Set unknown value x for verification
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assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
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assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
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Multiply #(.WIDTH(WIDTH)) MU (
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.a_re (mu_a_re), // i
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.a_im (mu_a_im), // i
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.b_re (tw_re ), // i
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.b_im (tw_im ), // i
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.m_re (mu_m_re), // o
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.m_im (mu_m_im) // o
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);
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always @(posedge clock) begin
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mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
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mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
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end
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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mu_do_en <= 1'b0;
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end else begin
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mu_do_en <= bf2_do_en;
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end
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end
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// No multiplication required at final stage
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assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
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assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
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assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
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endmodule
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