95 lines
3.4 KiB
Coq
95 lines
3.4 KiB
Coq
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//----------------------------------------------------------------------
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// SdfUnit2: Radix-2 SDF Dedicated for Twiddle Resolution M = 2
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//----------------------------------------------------------------------
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module SdfUnit2 #(
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parameter WIDTH = 16, // Data Bit Length
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parameter BF_RH = 0 // Butterfly Round Half Up
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)(
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input clock, // Master Clock
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input reset, // Active High Asynchronous Reset
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input di_en, // Input Data Enable
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input [WIDTH-1:0] di_re, // Input Data (Real)
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input [WIDTH-1:0] di_im, // Input Data (Imag)
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output reg do_en, // Output Data Enable
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output reg [WIDTH-1:0] do_re, // Output Data (Real)
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output reg [WIDTH-1:0] do_im // Output Data (Imag)
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);
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//----------------------------------------------------------------------
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// Internal Regs and Nets
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//----------------------------------------------------------------------
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reg bf_en; // Butterfly Add/Sub Enable
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wire[WIDTH-1:0] x0_re; // Data #0 to Butterfly (Real)
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wire[WIDTH-1:0] x0_im; // Data #0 to Butterfly (Imag)
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wire[WIDTH-1:0] x1_re; // Data #1 to Butterfly (Real)
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wire[WIDTH-1:0] x1_im; // Data #1 to Butterfly (Imag)
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wire[WIDTH-1:0] y0_re; // Data #0 from Butterfly (Real)
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wire[WIDTH-1:0] y0_im; // Data #0 from Butterfly (Imag)
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wire[WIDTH-1:0] y1_re; // Data #1 from Butterfly (Real)
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wire[WIDTH-1:0] y1_im; // Data #1 from Butterfly (Imag)
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wire[WIDTH-1:0] db_di_re; // Data to DelayBuffer (Real)
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wire[WIDTH-1:0] db_di_im; // Data to DelayBuffer (Imag)
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wire[WIDTH-1:0] db_do_re; // Data from DelayBuffer (Real)
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wire[WIDTH-1:0] db_do_im; // Data from DelayBuffer (Imag)
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wire[WIDTH-1:0] bf_sp_re; // Single-Path Data Output (Real)
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wire[WIDTH-1:0] bf_sp_im; // Single-Path Data Output (Imag)
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reg bf_sp_en; // Single-Path Data Enable
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//----------------------------------------------------------------------
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// Butterfly Add/Sub
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//----------------------------------------------------------------------
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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bf_en <= 1'b0;
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end else begin
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bf_en <= di_en ? ~bf_en : 1'b0;
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end
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end
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// Set unknown value x for verification
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assign x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
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assign x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
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assign x1_re = bf_en ? di_re : {WIDTH{1'bx}};
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assign x1_im = bf_en ? di_im : {WIDTH{1'bx}};
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Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
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.x0_re (x0_re ), // i
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.x0_im (x0_im ), // i
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.x1_re (x1_re ), // i
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.x1_im (x1_im ), // i
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.y0_re (y0_re ), // o
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.y0_im (y0_im ), // o
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.y1_re (y1_re ), // o
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.y1_im (y1_im ) // o
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);
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DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
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.clock (clock ), // i
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.di_re (db_di_re ), // i
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.di_im (db_di_im ), // i
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.do_re (db_do_re ), // o
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.do_im (db_do_im ) // o
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);
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assign db_di_re = bf_en ? y1_re : di_re;
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assign db_di_im = bf_en ? y1_im : di_im;
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assign bf_sp_re = bf_en ? y0_re : db_do_re;
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assign bf_sp_im = bf_en ? y0_im : db_do_im;
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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bf_sp_en <= 1'b0;
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do_en <= 1'b0;
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end else begin
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bf_sp_en <= di_en;
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do_en <= bf_sp_en;
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end
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end
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always @(posedge clock) begin
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do_re <= bf_sp_re;
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do_im <= bf_sp_im;
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end
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endmodule
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