195 lines
7.0 KiB
Tcl
195 lines
7.0 KiB
Tcl
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# TCL File Generated by Component Editor 20.1
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# Tue Jun 14 23:19:06 CEST 2022
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# DO NOT MODIFY
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#
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# data_channel "data_channel" v1.0
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# Johannes Kutning 2022.06.14.23:19:06
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# A data channel between two tasks
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module data_channel
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#
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set_module_property DESCRIPTION "A data channel between two tasks"
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set_module_property NAME data_channel
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP signal_processing
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set_module_property AUTHOR "Johannes Kutning"
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set_module_property DISPLAY_NAME data_channel
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL data_channel
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
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add_fileset_file data_channel.vhd VHDL PATH data_channel.vhd TOP_LEVEL_FILE
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add_fileset SIM_VHDL SIM_VHDL "" ""
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set_fileset_property SIM_VHDL TOP_LEVEL data_channel
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set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE true
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add_fileset_file data_channel.vhd VHDL PATH data_channel.vhd
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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#
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# connection point ctrl
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#
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add_interface ctrl avalon end
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set_interface_property ctrl addressUnits WORDS
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set_interface_property ctrl associatedClock clock
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set_interface_property ctrl associatedReset reset
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set_interface_property ctrl bitsPerSymbol 8
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set_interface_property ctrl burstOnBurstBoundariesOnly false
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set_interface_property ctrl burstcountUnits WORDS
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set_interface_property ctrl explicitAddressSpan 0
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set_interface_property ctrl holdTime 0
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set_interface_property ctrl linewrapBursts false
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set_interface_property ctrl maximumPendingReadTransactions 0
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set_interface_property ctrl maximumPendingWriteTransactions 0
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set_interface_property ctrl readLatency 0
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set_interface_property ctrl readWaitTime 1
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set_interface_property ctrl setupTime 0
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set_interface_property ctrl timingUnits Cycles
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set_interface_property ctrl writeWaitTime 0
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set_interface_property ctrl ENABLED true
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set_interface_property ctrl EXPORT_OF ""
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set_interface_property ctrl PORT_NAME_MAP ""
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set_interface_property ctrl CMSIS_SVD_VARIABLES ""
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set_interface_property ctrl SVD_ADDRESS_GROUP ""
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add_interface_port ctrl ctrl_address address Input 4
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add_interface_port ctrl ctrl_read read Input 1
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add_interface_port ctrl ctrl_readdata readdata Output 32
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add_interface_port ctrl ctrl_write write Input 1
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add_interface_port ctrl ctrl_writedata writedata Input 32
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set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
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set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point hw_sink
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#
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add_interface hw_sink avalon end
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set_interface_property hw_sink addressUnits WORDS
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set_interface_property hw_sink associatedClock clock
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set_interface_property hw_sink associatedReset reset
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set_interface_property hw_sink bitsPerSymbol 8
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set_interface_property hw_sink burstOnBurstBoundariesOnly false
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set_interface_property hw_sink burstcountUnits WORDS
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set_interface_property hw_sink explicitAddressSpan 0
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set_interface_property hw_sink holdTime 0
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set_interface_property hw_sink linewrapBursts false
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set_interface_property hw_sink maximumPendingReadTransactions 0
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set_interface_property hw_sink maximumPendingWriteTransactions 0
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set_interface_property hw_sink readLatency 0
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set_interface_property hw_sink readWaitTime 1
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set_interface_property hw_sink setupTime 0
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set_interface_property hw_sink timingUnits Cycles
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set_interface_property hw_sink writeWaitTime 0
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set_interface_property hw_sink ENABLED true
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set_interface_property hw_sink EXPORT_OF ""
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set_interface_property hw_sink PORT_NAME_MAP ""
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set_interface_property hw_sink CMSIS_SVD_VARIABLES ""
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set_interface_property hw_sink SVD_ADDRESS_GROUP ""
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add_interface_port hw_sink hw_sink_write write Input 1
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add_interface_port hw_sink hw_sink_writedata writedata Input 32
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set_interface_assignment hw_sink embeddedsw.configuration.isFlash 0
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set_interface_assignment hw_sink embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment hw_sink embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment hw_sink embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point hw_source
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#
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add_interface hw_source avalon end
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set_interface_property hw_source addressUnits WORDS
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set_interface_property hw_source associatedClock clock
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set_interface_property hw_source associatedReset reset
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set_interface_property hw_source bitsPerSymbol 8
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set_interface_property hw_source burstOnBurstBoundariesOnly false
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set_interface_property hw_source burstcountUnits WORDS
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set_interface_property hw_source explicitAddressSpan 0
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set_interface_property hw_source holdTime 0
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set_interface_property hw_source linewrapBursts false
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set_interface_property hw_source maximumPendingReadTransactions 0
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set_interface_property hw_source maximumPendingWriteTransactions 0
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set_interface_property hw_source readLatency 0
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set_interface_property hw_source readWaitTime 1
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set_interface_property hw_source setupTime 0
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set_interface_property hw_source timingUnits Cycles
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set_interface_property hw_source writeWaitTime 0
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set_interface_property hw_source ENABLED true
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set_interface_property hw_source EXPORT_OF ""
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set_interface_property hw_source PORT_NAME_MAP ""
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set_interface_property hw_source CMSIS_SVD_VARIABLES ""
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set_interface_property hw_source SVD_ADDRESS_GROUP ""
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add_interface_port hw_source hw_source_read read Input 1
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add_interface_port hw_source hw_source_readdata readdata Output 32
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set_interface_assignment hw_source embeddedsw.configuration.isFlash 0
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set_interface_assignment hw_source embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment hw_source embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment hw_source embeddedsw.configuration.isPrintableDevice 0
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