27 lines
610 B
VHDL
27 lines
610 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity data_sink_mux is
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port (
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sel : in std_logic;
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sw_write : in std_logic;
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sw_writedata : in std_logic_vector( 31 downto 0 );
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hw_write : in std_logic;
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hw_writedata : in std_logic_vector( 31 downto 0 );
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write : out std_logic;
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writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity data_sink_mux;
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architecture rtl of data_sink_mux is
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begin
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write <= sw_write when sel = '0' else hw_write;
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writedata <= sw_writedata when sel = '0' else
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hw_writedata;
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end architecture rtl;
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