27 lines
594 B
VHDL
27 lines
594 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity data_source_mux is
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port (
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sel : in std_logic;
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sw_read : in std_logic;
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sw_readdata : out std_logic_vector( 31 downto 0 );
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hw_read : in std_logic;
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hw_readdata : out std_logic_vector( 31 downto 0 );
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read : out std_logic;
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readdata : in std_logic_vector( 31 downto 0 )
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);
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end entity data_source_mux;
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architecture rtl of data_source_mux is
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begin
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read <= sw_read when sel = '0' else hw_read;
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sw_readdata <= readdata;
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hw_readdata <= readdata;
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end architecture rtl;
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