23 lines
677 B
VHDL
23 lines
677 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity hardware_task is
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port (
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clk : in std_logic;
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reset : in std_logic;
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ctrl_address : in std_logic_vector( 3 downto 0 );
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ctrl_read : in std_logic;
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ctrl_readdata : out std_logic_vector( 31 downto 0 );
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ctrl_write : in std_logic;
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ctrl_writedata : in std_logic_vector( 31 downto 0 );
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task_address : out std_logic_vector( 3 downto 0 );
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task_read : out std_logic;
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task_readdata : in std_logic_vector( 31 downto 0 );
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task_write : out std_logic;
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task_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity hardware_task;
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