120 lines
5.0 KiB
VHDL
120 lines
5.0 KiB
VHDL
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-- Component : squareRoot_pipe
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-- Author : pwkolas
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----------------------------------------------------------------------------------------------------
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-- File : squareRoot_pipe.vhd
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-- Mod. Date : XX.XX.XXXX
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-- Version : 1.00
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----------------------------------------------------------------------------------------------------
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-- Description : Square root calculator.
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-- Based on
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-- "A New Non-Restoring Square Root Algorithm and Its VLSI Implementations"
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--
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----------------------------------------------------------------------------------------------------
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-- Modification History :
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--
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----------------------------------------------------------------------------------------------------
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-- Comments :
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--
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----------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity squareRoot_pipe is
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generic (
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G_DATA_W : integer := 32
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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iv_data : in std_logic_vector(G_DATA_W-1 downto 0);
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ov_res : out std_logic_vector((G_DATA_W/2)-1 downto 0)
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);
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end entity squareRoot_pipe;
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architecture squareRoot_pipe_rtl of squareRoot_pipe is
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constant C_ALU_W : integer := ((G_DATA_W/2) + 2);
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constant C_PIPE_L : integer := G_DATA_W/2;
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constant C_OFFSET : integer := 3; -- width of start vectors going to ALU
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type t_arr_pipe_x_data is array (C_PIPE_L-1 downto 0) of unsigned(G_DATA_W-1 downto 0);
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signal a_data : t_arr_pipe_x_data; -- (D)
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signal a_R : t_arr_pipe_x_data; -- (R)
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type t_arr_pipe_x_alu is array (C_PIPE_L-1 downto 0) of unsigned(C_ALU_W-1 downto 0);
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type t_arr_pipe_x_res is array (C_PIPE_L-1 downto 0) of unsigned(G_DATA_W/2-1 downto 0);
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signal a_Q : t_arr_pipe_x_res; -- (ALU Q out)
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signal nextOp : std_logic_vector(C_PIPE_L-1 downto 0);
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begin
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sqrt_p : process (clk, rst)
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variable va_AluInR : t_arr_pipe_x_alu; -- (ALU R in)
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variable va_AluInQ : t_arr_pipe_x_alu; -- (ALU Q in)
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variable va_AluOut : t_arr_pipe_x_alu; -- (ALU Q out)
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begin
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if (rst = '1') then
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a_data <= (others => (others => '0'));
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a_R <= (others => (others => '0'));
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a_Q <= (others => (others => '0'));
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va_AluInR := (others => (others => '0'));
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va_AluInQ := (others => (others => '0'));
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va_AluOut := (others => (others => '0'));
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nextOp <= (others => '0');
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elsif rising_edge(clk) then
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-- stage 0 start conditions, ALU inputs
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va_AluInR(0) := (others => '0');
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va_AluInR(0)(1 downto 0) := unsigned(iv_data(G_DATA_W-1 downto G_DATA_W-1-1));
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va_AluInQ(0) := (others => '0');
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va_AluInQ(0)(0) := '1';
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-- stage 0 calculations
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va_AluOut(0) := va_AluInR(0) - va_AluInQ(0);
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-- stage 0 result registers, ALU output
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a_data(0) <= shift_left(unsigned(iv_data), 2);
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a_R(0) <= (others => '0');
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a_R(0)(G_DATA_W-1 downto G_DATA_W-1-1) <= va_AluOut(0)(1 downto 0);
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a_Q(0) <= (others => '0');
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a_Q(0)(0) <= not va_AluOut(0)(2);
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nextOp(0) <= not va_AluOut(0)(2);
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-- next stages
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for i in 1 to C_PIPE_L-1 loop
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-- prepare inputs for next stage
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va_AluInR(i) := (others => '0');
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va_AluInR(i)(C_OFFSET+i-1 downto 2) := a_R(i-1)(G_DATA_W-(i-1)-1 downto G_DATA_W-(2*i));
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va_AluInR(i)(2-1 downto 0) := a_data(i-1)(G_DATA_W-1 downto G_DATA_W-1-1);
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va_AluInQ(i) := (others => '0');
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va_AluInQ(i)(C_OFFSET+(i-1)-1 downto 2) := a_Q(i-1)(i-1 downto 0);
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va_AluInQ(i)(1) := not a_Q(i-1)(0);
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va_AluInQ(i)(0) := '1';
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-- ALU ADD/SUB
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if (nextOp(i-1) = '1') then
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va_AluOut(i) := va_AluInR(i) - va_AluInQ(i);
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else
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va_AluOut(i) := va_AluInR(i) + va_AluInQ(i);
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end if;
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-- result registers
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a_data(i) <= shift_left(unsigned(a_data(i-1)), 2);
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a_R(i) <= (others => '0');
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a_R(i)(G_DATA_W-i-1 downto G_DATA_W-2*(i+1)) <= va_AluOut(i)(i+1 downto 0);
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a_Q(i) <= shift_left(unsigned(a_Q(i-1)), 1);
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a_Q(i)(0) <= not va_AluOut(i)(i+2);
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nextOp(i) <= not va_AluOut(i)(i+2);
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end loop;
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end if;
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end process;
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ov_res <= std_logic_vector(a_Q(C_PIPE_L-1));
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end architecture squareRoot_pipe_rtl;
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