42 lines
1.1 KiB
VHDL
42 lines
1.1 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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package task is
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type State is (
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TASK_IDLE,
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TASK_RUNNING,
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TASK_DONE
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);
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function to_std_logic_vector( s : State; len : positive ) return std_logic_vector;
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constant STREAM_LEN : integer := 1024;
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end package task;
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package body task is
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function to_std_logic_vector( s : State; len : positive ) return std_logic_vector is
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constant MIN_LEN : positive := positive( ceil( log2( real( State'pos( State'right ) + 1 ) ) ) );
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variable vector : std_logic_vector( MIN_LEN - 1 downto 0 );
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variable output : std_logic_vector( len - 1 downto 0 );
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begin
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vector := std_logic_vector( to_unsigned( State'pos( s ), MIN_LEN ) );
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if ( len < MIN_LEN ) then
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output := ( others => 'U' );
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elsif ( len = MIN_LEN ) then
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output := vector;
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else
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output := ( others => '0' );
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output( vector'range ) := vector;
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end if;
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return output;
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end function to_std_logic_vector;
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end package body task;
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