66 lines
1.6 KiB
VHDL
66 lines
1.6 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity task_sine is
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port (
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clk : in std_logic;
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reset : in std_logic;
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address : in std_logic_vector( 3 downto 0 );
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read : in std_logic;
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readdata : out std_logic_vector( 31 downto 0 );
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write : in std_logic;
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writedata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity task_sine;
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architecture struct of task_sine is
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signal task_start : std_logic;
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signal task_state : work.task.State := work.task.TASK_IDLE;
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signal task_config : work.reg32.RegArray( 0 to 2 );
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begin
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u_control: entity work.hardware_task_control
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port map (
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clk => clk,
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reset => reset,
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address => address,
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read => read,
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readdata => readdata,
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write => write,
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writedata => writedata,
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task_start => task_start,
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task_state => task_state,
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task_config => task_config
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);
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u_sine: entity work.sine
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port map (
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clk => clk,
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reset => reset,
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task_start => task_start,
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task_state => task_state,
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step_size => task_config( 0 ),
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phase => task_config( 1 ),
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amplitude => task_config( 2 ),
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signal_write => signal_write,
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signal_writedata => signal_writedata
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);
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end architecture struct;
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