121 lines
3.7 KiB
Tcl
121 lines
3.7 KiB
Tcl
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# TCL File Generated by Component Editor 21.1
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# Thu Sep 08 23:25:06 CEST 2022
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# DO NOT MODIFY
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#
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# hardware_timestamp "hardware_timestamp" v1.0
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# Johannes Kutning 2022.09.08.23:25:06
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# Timestamp device used to measure software execution time
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module hardware_timestamp
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#
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set_module_property DESCRIPTION "Timestamp device used to measure software execution time"
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set_module_property NAME hardware_timestamp
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP signal_processing
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set_module_property AUTHOR "Johannes Kutning"
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set_module_property DISPLAY_NAME hardware_timestamp
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL timer
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file hardware_timestamp.vhd VHDL PATH hardware/system/hardware_timestamp.vhd TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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#
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# connection point ctrl
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#
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add_interface ctrl avalon end
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set_interface_property ctrl addressUnits WORDS
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set_interface_property ctrl associatedClock clock
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set_interface_property ctrl associatedReset reset
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set_interface_property ctrl bitsPerSymbol 8
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set_interface_property ctrl burstOnBurstBoundariesOnly false
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set_interface_property ctrl burstcountUnits WORDS
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set_interface_property ctrl explicitAddressSpan 0
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set_interface_property ctrl holdTime 0
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set_interface_property ctrl linewrapBursts false
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set_interface_property ctrl maximumPendingReadTransactions 0
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set_interface_property ctrl maximumPendingWriteTransactions 0
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set_interface_property ctrl readLatency 0
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set_interface_property ctrl readWaitTime 1
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set_interface_property ctrl setupTime 0
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set_interface_property ctrl timingUnits Cycles
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set_interface_property ctrl writeWaitTime 0
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set_interface_property ctrl ENABLED true
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set_interface_property ctrl EXPORT_OF ""
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set_interface_property ctrl PORT_NAME_MAP ""
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set_interface_property ctrl CMSIS_SVD_VARIABLES ""
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set_interface_property ctrl SVD_ADDRESS_GROUP ""
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add_interface_port ctrl address address Input 4
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add_interface_port ctrl read read Input 1
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add_interface_port ctrl readdata readdata Output 32
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add_interface_port ctrl write write Input 1
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add_interface_port ctrl writedata writedata Input 32
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set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
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set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
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