64 lines
1.4 KiB
Makefile
64 lines
1.4 KiB
Makefile
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#
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#
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#
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#
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# Make sure that the top level is assigned to main
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$(if $(main),,\
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$(error Assign top level entity name to variable "main"))
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# Make sure that at least on vhdl source is assigned
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$(if $(vhdl_srcs),,\
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$(error Assign at least on vhdl source to variable "vhdl_srcs"))
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# Append prefix -d to all generics
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generics = $(addprefix -g,$(generics))
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# Add VHDL 2008 as default build standard
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vhdl_flags += -2008
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vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
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verilog_objs = $(verilog_srcs:.v=.vo)
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assert_level := error
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.PHONY: sim clean
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sim: ${verilog_objs} ${vhdl_objs}
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@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -voptargs=+acc -c work.${main} -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" \
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| ../../scripts/highlight_test_results.sh
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gui: ${verilog_objs} ${vhdl_objs}
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@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -gGUI_MODE=true -voptargs=+acc work.${main} -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all"
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%.vo: %.v .libwork
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@echo "Analysing $<"
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@vlog -work work ${verilog_flags} $<
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%.vhdo: %.vhd .libwork
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@echo "Analysing $<"
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@vcom -work work ${vhdl_flags} $<
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.libwork:
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@vlib work && vmap work work && touch $@
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clean:
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@rm -rf work \
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.libwork \
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transcript \
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modelsim.ini \
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vlog.opt \
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vsim.wlf \
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data.py \
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data.pyc \
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help:
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@echo Use ghdl to simulate and synthesis a vhdl design.
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@echo
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@echo Build configuration variables:
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@echo main main entity
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@echo vhdl_flags
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@echo generics
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