signal_processing_vorlage/hardware/signal_processing/rand.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity rand is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;
        seed : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity rand;

architecture rtl of rand is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
	signal lfsr : std_logic_vector( 31 downto 0 );
	signal lfsr_next : std_logic_vector( 31 downto 0 );
	signal bitte : std_logic;
	signal exponent : std_logic_vector( 7 downto 0 );
	signal ieee754 : std_logic_vector( 31 downto 0 );

begin
    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

	exponent <= std_logic_vector(to_unsigned(128, 8) + unsigned(lfsr(23 downto 23))) when (lfsr(30) = '1')
		else std_logic_vector(to_unsigned(124, 8) + unsigned(lfsr(24 downto 23)));

	ieee754 <= lfsr(31) & exponent(7 downto 0) & lfsr(22 downto 0);

	bitte <= (lfsr(31) XOR lfsr(21) XOR lfsr(1));
	lfsr_next <= lfsr(30 downto 0) & bitte;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
			-- alle Signale in der Reset Bedingung initialisieren
			lfsr <= seed;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
		        when work.task.TASK_IDLE =>
		            index <= 0;
		            signal_write <= '0';

					lfsr <= seed;
		        when work.task.TASK_RUNNING =>
		            signal_write <= '1';
		            signal_writedata <= ( ieee754 );

					lfsr <= lfsr_next;
				    index <= index + 1;

		        when work.task.TASK_DONE =>
		            index <= 0;
		            signal_write <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;