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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.float.all;
use work.task.all;
entity sine is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
step_size : in work.reg32.word;
phase : in work.reg32.word;
amplitude : in work.reg32.word;
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity sine;
architecture rtl of sine is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
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type CalcState is (
CALC_IDLE,
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CALC_ANGLE,
CALC_START,
CALC_BUSY,
CALC_WRITE,
CALC_DONE
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);
signal Calc_State : CalcState;
signal data_valid_ipcore : std_logic;
signal busy_ipcore : std_logic;
signal result_valid_ipcore : std_logic;
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signal angle_ipcore : signed(31 downto 0);
signal step_size_adapted : std_logic_vector( 31 downto 0 );
signal sine_amplitude : signed(31 downto 0);
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signal sine_ipcore : signed(31 downto 0);
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begin
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u_float_sine: entity work.float_sine
generic map(
ITERATIONS => 8
)
port map(
clk => clk,
reset => reset,
data_valid => data_valid_ipcore,
busy => busy_ipcore,
result_valid => result_valid_ipcore,
-- " TODO Check if this is allowed (direkt access to maped signal)"
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angle => angle_ipcore,
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sine => sine_ipcore
);
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task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN ) then
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next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
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Calc_State <= CALC_IDLE;
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index <= 0;
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signal_write <= '0';
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elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
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when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
Calc_State <= CALC_IDLE;
when work.task.TASK_RUNNING =>
case Calc_State is
when CALC_IDLE =>
angle_ipcore <= SIGNED(phase);
Calc_State <= CALC_START;
when CALC_ANGLE =>
angle_ipcore <= (angle_ipcore + (SIGNED(step_size_adapted)));
Calc_State <= CALC_START;
when CALC_START =>
data_valid_ipcore <= '1';
if(busy_ipcore = '1') then
Calc_State <= CALC_BUSY;
end if;
when CALC_BUSY =>
data_valid_ipcore <= '0';
if(result_valid_ipcore = '1') then
Calc_State <= CALC_WRITE;
end if;
when CALC_WRITE =>
-- sine_amplitude <= sine_ipcore(30 downto 23) + (signed(amplitude))(30 downto 23) - "127";
sine_amplitude <= sine_ipcore(31 downto 31) & (sine_ipcore(30 downto 23) + (signed(amplitude(30 downto 23)) - 127)) & sine_ipcore(22 downto 0);
-- sine_amplitude <= STD_LOGIC_VECTOR(sine_ipcore(30 downto 23)) + STD_LOGIC_VECTOR(amplitude(30 downto 23)) - "127";
signal_write <= '1';
Calc_State <= CALC_DONE;
when CALC_DONE =>
signal_write <= '0';
index <= index + 1;
Calc_State <= CALC_ANGLE;
end case;
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
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end case;
end if;
end process sync;
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signal_writedata <= STD_LOGIC_VECTOR(sine_amplitude);
--step_size_adapted <= (step_size(31-5 downto 0) & "00000");
step_size_adapted <= (step_size );
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task_state <= current_task_state;
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-- #TODO phase_ipcore <= (SIGNED(phase));
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end architecture rtl;