Versuch 3 CRC Hardware vorlaeufig

hardware/signal_processing/crc.vhd

@@ -28,7 +28,41 @@ architecture rtl of crc is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	--Selbst angelegte Signale
+	signal data_valid_flag : std_logic;
+	signal busy_flag : std_logic;
+	signal result_valid_flag : std_logic;
+	signal crc_vorher : signed( 31 downto 0);
+	signal crc_nachher :  signed( 31 downto 0 );
+	signal komplett_ergebnis : signed( 31 downto 0 ); --Ergebnis muss zum Schluss evtl invertiert werden (siehe Software)
+	signal wort : signed( 31 downto 0 );
+	signal byte : signed(  7 downto 0 );
+
+	--Zustände für die Zustandsmaschine für die Berechnung
+	type CalcState is (
+		CALC_IDLE,
+		CALC_START,
+		CALC_CRC,
+		CALC_STORE_RESULT
+	);
+	--Signale für die Zustandsmaschine für die Berechnung
+	signal current_calc_state : CalcState;
+	signal next_calc_state : CalcState;
+
+
+	-- Anmerkung zu CRC-Polynom:
+	-- in Software wurde 	0xEDB88320		CRC-32 Polynom (Invers) verwendet
+	-- nicht invers waere 	0x04C11DB7
 begin
+	-- Eigener Core verwendet 0xEDB88320 als Polynom
+	u_crc_core : entity work.crc_core					-- Das hier ist der Core
+	port map (
+		crcIn	=>	,	--in std_logic_vector(31 downto 0)
+		data	=>	,	--in std_logic_vector(7 downto 0);
+		crcOut	=>		--out std_logic_vector(31 downto 0)
+	);
+
+	-- Diesen Prozess nicht aendern
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -48,6 +82,31 @@ begin
         end case;
     end process task_state_transitions;
 
+	--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Nur aus sine.vhd kopiert!
+	calc_state_transitions: process (all) is
+	begin
+		next_calc_state <= current_calc_state; 
+		case current_calc_state is
+			when CALC_IDLE=>
+				if (current_task_state= work.task.TASK_RUNNING) then 
+					next_calc_state <= CALC_START;
+				end if;
+			when CALC_START=>
+				next_calc_state <= CALC_CRC;
+			when CALC_CRC =>
+				if (result_valid_flag = '1' and busy_flag = '0') then 	--or falling_edge( busy) ?
+					next_calc_state <= CALC_STORE_RESULT;
+				end if;
+			when CALC_STORE_RESULT =>
+				if ( index = work.task.STREAM_LEN ) then
+					next_calc_state <= CALC_IDLE;
+				else
+					next_calc_state <= CALC_START;
+				end if;
+		end case;
+	end process calc_state_transitions;
+
+	--Dieser Prozess war vorher schon drin, muss aber noch modifiziert werden
     sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
@@ -58,18 +117,56 @@ begin
             case next_task_state is
             when work.task.TASK_IDLE =>
                 index <= 0;
-                signal_write <= '0';
+                -- signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
+                index <= index + 1;	
+                --signal_write <= '1';
+                --signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
                 index <= 0;
-                signal_write <= '0';
+                --signal_write <= '0';
             end case;
         end if;
     end process sync;
 
+		crc_calc :process ( clk, reset ) is
+	begin
+        if ( reset = '1' ) then
+        	signal_read <= '0';
+			signal_write <= '0';
+			signal_writedata <= (others => '0');
+			flag_index <= '0';
+        elsif ( rising_edge( clk ) ) then
+			case crc_state is	--current oder next_calc_state
+			when 0 =>
+				signal_write <= '0';
+				flag_index <= '0';
+				if ( current_task_state = work.task.TASK_RUNNING ) then
+					signal_read <= '1';
+					crc_state <= 1;	--Calc Zustand aendern. Sollte ueber Uebergangsschaltnetz geregelt werden
+				end if;
+			when 1 =>
+				signal_read <= '0';
+				--Berechne hier crc_out
+				--Einfacher als Berechnung mit IP Core waere genau hier den ganzen Code davon reinkopieren
+
+				crc_state <= 2;		--Calc Zustand aendern
+			when 2 =>
+				if ( current_task_state = work.task.TASK_DONE ) then
+					signal_writedata <= not(crc_out);	--Ergebnis invertieren
+					signal_write <= '1';
+				end if;		
+				
+				flag_index <= '1';	--flag_index sagt nur, dass der index hochgezaehlt werden soll
+				crc_state <= 0;		--Calc Zustand aendern
+				-- assign new crc value
+ 				crc_in <= crc_out;
+
+			end case;
+		end if;
+	end process crc_calc;
+
+
     task_state <= current_task_state;
 
 end architecture rtl;