Versuch 3 CRC Hardware vorlaeufig
This commit is contained in:
brandlfl78731
parent
118d08219e
commit
509e01e501
@ -28,7 +28,41 @@ architecture rtl of crc is
|
|||||||
signal next_task_state : work.task.State;
|
signal next_task_state : work.task.State;
|
||||||
signal index : integer range 0 to work.task.STREAM_LEN;
|
signal index : integer range 0 to work.task.STREAM_LEN;
|
||||||
|
|
||||||
|
--Selbst angelegte Signale
|
||||||
|
signal data_valid_flag : std_logic;
|
||||||
|
signal busy_flag : std_logic;
|
||||||
|
signal result_valid_flag : std_logic;
|
||||||
|
signal crc_vorher : signed( 31 downto 0);
|
||||||
|
signal crc_nachher : signed( 31 downto 0 );
|
||||||
|
signal komplett_ergebnis : signed( 31 downto 0 ); --Ergebnis muss zum Schluss evtl invertiert werden (siehe Software)
|
||||||
|
signal wort : signed( 31 downto 0 );
|
||||||
|
signal byte : signed( 7 downto 0 );
|
||||||
|
|
||||||
|
--Zustände für die Zustandsmaschine für die Berechnung
|
||||||
|
type CalcState is (
|
||||||
|
CALC_IDLE,
|
||||||
|
CALC_START,
|
||||||
|
CALC_CRC,
|
||||||
|
CALC_STORE_RESULT
|
||||||
|
);
|
||||||
|
--Signale für die Zustandsmaschine für die Berechnung
|
||||||
|
signal current_calc_state : CalcState;
|
||||||
|
signal next_calc_state : CalcState;
|
||||||
|
|
||||||
|
|
||||||
|
-- Anmerkung zu CRC-Polynom:
|
||||||
|
-- in Software wurde 0xEDB88320 CRC-32 Polynom (Invers) verwendet
|
||||||
|
-- nicht invers waere 0x04C11DB7
|
||||||
begin
|
begin
|
||||||
|
-- Eigener Core verwendet 0xEDB88320 als Polynom
|
||||||
|
u_crc_core : entity work.crc_core -- Das hier ist der Core
|
||||||
|
port map (
|
||||||
|
crcIn => , --in std_logic_vector(31 downto 0)
|
||||||
|
data => , --in std_logic_vector(7 downto 0);
|
||||||
|
crcOut => --out std_logic_vector(31 downto 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Diesen Prozess nicht aendern
|
||||||
task_state_transitions : process ( current_task_state, task_start, index ) is
|
task_state_transitions : process ( current_task_state, task_start, index ) is
|
||||||
begin
|
begin
|
||||||
next_task_state <= current_task_state;
|
next_task_state <= current_task_state;
|
||||||
@ -48,6 +82,31 @@ begin
|
|||||||
end case;
|
end case;
|
||||||
end process task_state_transitions;
|
end process task_state_transitions;
|
||||||
|
|
||||||
|
--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Nur aus sine.vhd kopiert!
|
||||||
|
calc_state_transitions: process (all) is
|
||||||
|
begin
|
||||||
|
next_calc_state <= current_calc_state;
|
||||||
|
case current_calc_state is
|
||||||
|
when CALC_IDLE=>
|
||||||
|
if (current_task_state= work.task.TASK_RUNNING) then
|
||||||
|
next_calc_state <= CALC_START;
|
||||||
|
end if;
|
||||||
|
when CALC_START=>
|
||||||
|
next_calc_state <= CALC_CRC;
|
||||||
|
when CALC_CRC =>
|
||||||
|
if (result_valid_flag = '1' and busy_flag = '0') then --or falling_edge( busy) ?
|
||||||
|
next_calc_state <= CALC_STORE_RESULT;
|
||||||
|
end if;
|
||||||
|
when CALC_STORE_RESULT =>
|
||||||
|
if ( index = work.task.STREAM_LEN ) then
|
||||||
|
next_calc_state <= CALC_IDLE;
|
||||||
|
else
|
||||||
|
next_calc_state <= CALC_START;
|
||||||
|
end if;
|
||||||
|
end case;
|
||||||
|
end process calc_state_transitions;
|
||||||
|
|
||||||
|
--Dieser Prozess war vorher schon drin, muss aber noch modifiziert werden
|
||||||
sync : process ( clk, reset ) is
|
sync : process ( clk, reset ) is
|
||||||
begin
|
begin
|
||||||
if ( reset = '1' ) then
|
if ( reset = '1' ) then
|
||||||
@ -58,18 +117,56 @@ begin
|
|||||||
case next_task_state is
|
case next_task_state is
|
||||||
when work.task.TASK_IDLE =>
|
when work.task.TASK_IDLE =>
|
||||||
index <= 0;
|
index <= 0;
|
||||||
signal_write <= '0';
|
-- signal_write <= '0';
|
||||||
when work.task.TASK_RUNNING =>
|
when work.task.TASK_RUNNING =>
|
||||||
index <= index + 1;
|
index <= index + 1;
|
||||||
signal_write <= '1';
|
--signal_write <= '1';
|
||||||
signal_writedata <= ( others => '0' );
|
--signal_writedata <= ( others => '0' );
|
||||||
when work.task.TASK_DONE =>
|
when work.task.TASK_DONE =>
|
||||||
index <= 0;
|
index <= 0;
|
||||||
signal_write <= '0';
|
--signal_write <= '0';
|
||||||
end case;
|
end case;
|
||||||
end if;
|
end if;
|
||||||
end process sync;
|
end process sync;
|
||||||
|
|
||||||
|
crc_calc :process ( clk, reset ) is
|
||||||
|
begin
|
||||||
|
if ( reset = '1' ) then
|
||||||
|
signal_read <= '0';
|
||||||
|
signal_write <= '0';
|
||||||
|
signal_writedata <= (others => '0');
|
||||||
|
flag_index <= '0';
|
||||||
|
elsif ( rising_edge( clk ) ) then
|
||||||
|
case crc_state is --current oder next_calc_state
|
||||||
|
when 0 =>
|
||||||
|
signal_write <= '0';
|
||||||
|
flag_index <= '0';
|
||||||
|
if ( current_task_state = work.task.TASK_RUNNING ) then
|
||||||
|
signal_read <= '1';
|
||||||
|
crc_state <= 1; --Calc Zustand aendern. Sollte ueber Uebergangsschaltnetz geregelt werden
|
||||||
|
end if;
|
||||||
|
when 1 =>
|
||||||
|
signal_read <= '0';
|
||||||
|
--Berechne hier crc_out
|
||||||
|
--Einfacher als Berechnung mit IP Core waere genau hier den ganzen Code davon reinkopieren
|
||||||
|
|
||||||
|
crc_state <= 2; --Calc Zustand aendern
|
||||||
|
when 2 =>
|
||||||
|
if ( current_task_state = work.task.TASK_DONE ) then
|
||||||
|
signal_writedata <= not(crc_out); --Ergebnis invertieren
|
||||||
|
signal_write <= '1';
|
||||||
|
end if;
|
||||||
|
|
||||||
|
flag_index <= '1'; --flag_index sagt nur, dass der index hochgezaehlt werden soll
|
||||||
|
crc_state <= 0; --Calc Zustand aendern
|
||||||
|
-- assign new crc value
|
||||||
|
crc_in <= crc_out;
|
||||||
|
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end process crc_calc;
|
||||||
|
|
||||||
|
|
||||||
task_state <= current_task_state;
|
task_state <= current_task_state;
|
||||||
|
|
||||||
end architecture rtl;
|
end architecture rtl;
|
||||||
|
|||||||
69
hardware/system/crc_core.vhd
Normal file
69
hardware/system/crc_core.vhd
Normal file
@ -0,0 +1,69 @@
|
|||||||
|
-- vim: ts=4 sw=4 expandtab
|
||||||
|
|
||||||
|
-- THIS IS GENERATED VHDL CODE.
|
||||||
|
-- https://bues.ch/h/crcgen
|
||||||
|
--
|
||||||
|
-- This code is Public Domain.
|
||||||
|
-- Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
-- purpose with or without fee is hereby granted.
|
||||||
|
--
|
||||||
|
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||||
|
-- SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
|
||||||
|
-- RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
|
||||||
|
-- NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
|
||||||
|
-- USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
|
||||||
|
-- CRC polynomial coefficients: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
|
||||||
|
-- 0xEDB88320 (hex)
|
||||||
|
-- CRC width: 32 bits
|
||||||
|
-- CRC shift direction: right (little endian)
|
||||||
|
-- Input word width: 8 bits
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity crc_core is
|
||||||
|
port (
|
||||||
|
crcIn: in std_logic_vector(31 downto 0);
|
||||||
|
data: in std_logic_vector(7 downto 0);
|
||||||
|
crcOut: out std_logic_vector(31 downto 0)
|
||||||
|
);
|
||||||
|
end entity crc_core;
|
||||||
|
|
||||||
|
architecture Behavioral of crc_core is
|
||||||
|
begin
|
||||||
|
crcOut(0) <= crcIn(2) xor crcIn(8) xor data(2);
|
||||||
|
crcOut(1) <= crcIn(0) xor crcIn(3) xor crcIn(9) xor data(0) xor data(3);
|
||||||
|
crcOut(2) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(10) xor data(0) xor data(1) xor data(4);
|
||||||
|
crcOut(3) <= crcIn(1) xor crcIn(2) xor crcIn(5) xor crcIn(11) xor data(1) xor data(2) xor data(5);
|
||||||
|
crcOut(4) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(6) xor crcIn(12) xor data(0) xor data(2) xor data(3) xor data(6);
|
||||||
|
crcOut(5) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(7) xor crcIn(13) xor data(1) xor data(3) xor data(4) xor data(7);
|
||||||
|
crcOut(6) <= crcIn(4) xor crcIn(5) xor crcIn(14) xor data(4) xor data(5);
|
||||||
|
crcOut(7) <= crcIn(0) xor crcIn(5) xor crcIn(6) xor crcIn(15) xor data(0) xor data(5) xor data(6);
|
||||||
|
crcOut(8) <= crcIn(1) xor crcIn(6) xor crcIn(7) xor crcIn(16) xor data(1) xor data(6) xor data(7);
|
||||||
|
crcOut(9) <= crcIn(7) xor crcIn(17) xor data(7);
|
||||||
|
crcOut(10) <= crcIn(2) xor crcIn(18) xor data(2);
|
||||||
|
crcOut(11) <= crcIn(3) xor crcIn(19) xor data(3);
|
||||||
|
crcOut(12) <= crcIn(0) xor crcIn(4) xor crcIn(20) xor data(0) xor data(4);
|
||||||
|
crcOut(13) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(21) xor data(0) xor data(1) xor data(5);
|
||||||
|
crcOut(14) <= crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(22) xor data(1) xor data(2) xor data(6);
|
||||||
|
crcOut(15) <= crcIn(2) xor crcIn(3) xor crcIn(7) xor crcIn(23) xor data(2) xor data(3) xor data(7);
|
||||||
|
crcOut(16) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(24) xor data(0) xor data(2) xor data(3) xor data(4);
|
||||||
|
crcOut(17) <= crcIn(0) xor crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(25) xor data(0) xor data(1) xor data(3) xor data(4) xor data(5);
|
||||||
|
crcOut(18) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(26) xor data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6);
|
||||||
|
crcOut(19) <= crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(27) xor data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7);
|
||||||
|
crcOut(20) <= crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(28) xor data(3) xor data(4) xor data(6) xor data(7);
|
||||||
|
crcOut(21) <= crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(29) xor data(2) xor data(4) xor data(5) xor data(7);
|
||||||
|
crcOut(22) <= crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(30) xor data(2) xor data(3) xor data(5) xor data(6);
|
||||||
|
crcOut(23) <= crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(31) xor data(3) xor data(4) xor data(6) xor data(7);
|
||||||
|
crcOut(24) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor data(0) xor data(2) xor data(4) xor data(5) xor data(7);
|
||||||
|
crcOut(25) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor data(0) xor data(1) xor data(2) xor data(3) xor data(5) xor data(6);
|
||||||
|
crcOut(26) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(6) xor data(7);
|
||||||
|
crcOut(27) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor data(1) xor data(3) xor data(4) xor data(5) xor data(7);
|
||||||
|
crcOut(28) <= crcIn(0) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor data(0) xor data(4) xor data(5) xor data(6);
|
||||||
|
crcOut(29) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor data(0) xor data(1) xor data(5) xor data(6) xor data(7);
|
||||||
|
crcOut(30) <= crcIn(0) xor crcIn(1) xor crcIn(6) xor crcIn(7) xor data(0) xor data(1) xor data(6) xor data(7);
|
||||||
|
crcOut(31) <= crcIn(1) xor crcIn(7) xor data(1) xor data(7);
|
||||||
|
end architecture Behavioral;
|
||||||
Loading…
x
Reference in New Issue
Block a user