Versuch 3 CRC Hardware vorlaeufig
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brandlfl78731
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@ -28,7 +28,41 @@ architecture rtl of crc is
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--Selbst angelegte Signale
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signal data_valid_flag : std_logic;
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signal busy_flag : std_logic;
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signal result_valid_flag : std_logic;
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signal crc_vorher : signed( 31 downto 0);
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signal crc_nachher : signed( 31 downto 0 );
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signal komplett_ergebnis : signed( 31 downto 0 ); --Ergebnis muss zum Schluss evtl invertiert werden (siehe Software)
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signal wort : signed( 31 downto 0 );
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signal byte : signed( 7 downto 0 );
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--Zustände für die Zustandsmaschine für die Berechnung
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type CalcState is (
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CALC_IDLE,
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CALC_START,
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CALC_CRC,
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CALC_STORE_RESULT
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);
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--Signale für die Zustandsmaschine für die Berechnung
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signal current_calc_state : CalcState;
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signal next_calc_state : CalcState;
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-- Anmerkung zu CRC-Polynom:
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-- in Software wurde 0xEDB88320 CRC-32 Polynom (Invers) verwendet
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-- nicht invers waere 0x04C11DB7
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begin
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-- Eigener Core verwendet 0xEDB88320 als Polynom
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u_crc_core : entity work.crc_core -- Das hier ist der Core
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port map (
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crcIn => , --in std_logic_vector(31 downto 0)
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data => , --in std_logic_vector(7 downto 0);
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crcOut => --out std_logic_vector(31 downto 0)
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);
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-- Diesen Prozess nicht aendern
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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@ -48,6 +82,31 @@ begin
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end case;
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end process task_state_transitions;
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--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Nur aus sine.vhd kopiert!
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calc_state_transitions: process (all) is
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begin
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next_calc_state <= current_calc_state;
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case current_calc_state is
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when CALC_IDLE=>
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if (current_task_state= work.task.TASK_RUNNING) then
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next_calc_state <= CALC_START;
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end if;
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when CALC_START=>
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next_calc_state <= CALC_CRC;
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when CALC_CRC =>
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if (result_valid_flag = '1' and busy_flag = '0') then --or falling_edge( busy) ?
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next_calc_state <= CALC_STORE_RESULT;
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end if;
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when CALC_STORE_RESULT =>
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if ( index = work.task.STREAM_LEN ) then
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next_calc_state <= CALC_IDLE;
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else
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next_calc_state <= CALC_START;
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end if;
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end case;
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end process calc_state_transitions;
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--Dieser Prozess war vorher schon drin, muss aber noch modifiziert werden
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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@ -58,18 +117,56 @@ begin
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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-- signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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--signal_write <= '1';
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--signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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--signal_write <= '0';
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end case;
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end if;
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end process sync;
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crc_calc :process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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signal_read <= '0';
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signal_write <= '0';
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signal_writedata <= (others => '0');
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flag_index <= '0';
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elsif ( rising_edge( clk ) ) then
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case crc_state is --current oder next_calc_state
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when 0 =>
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signal_write <= '0';
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flag_index <= '0';
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if ( current_task_state = work.task.TASK_RUNNING ) then
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signal_read <= '1';
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crc_state <= 1; --Calc Zustand aendern. Sollte ueber Uebergangsschaltnetz geregelt werden
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end if;
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when 1 =>
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signal_read <= '0';
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--Berechne hier crc_out
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--Einfacher als Berechnung mit IP Core waere genau hier den ganzen Code davon reinkopieren
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crc_state <= 2; --Calc Zustand aendern
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when 2 =>
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if ( current_task_state = work.task.TASK_DONE ) then
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signal_writedata <= not(crc_out); --Ergebnis invertieren
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signal_write <= '1';
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end if;
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flag_index <= '1'; --flag_index sagt nur, dass der index hochgezaehlt werden soll
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crc_state <= 0; --Calc Zustand aendern
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-- assign new crc value
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crc_in <= crc_out;
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end case;
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end if;
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end process crc_calc;
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task_state <= current_task_state;
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end architecture rtl;
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69
hardware/system/crc_core.vhd
Normal file
69
hardware/system/crc_core.vhd
Normal file
@ -0,0 +1,69 @@
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-- vim: ts=4 sw=4 expandtab
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-- THIS IS GENERATED VHDL CODE.
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-- https://bues.ch/h/crcgen
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--
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-- This code is Public Domain.
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-- Permission to use, copy, modify, and/or distribute this software for any
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-- purpose with or without fee is hereby granted.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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-- SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
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-- RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
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-- NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
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-- USE OR PERFORMANCE OF THIS SOFTWARE.
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-- CRC polynomial coefficients: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
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-- 0xEDB88320 (hex)
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-- CRC width: 32 bits
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-- CRC shift direction: right (little endian)
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-- Input word width: 8 bits
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity crc_core is
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port (
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crcIn: in std_logic_vector(31 downto 0);
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data: in std_logic_vector(7 downto 0);
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crcOut: out std_logic_vector(31 downto 0)
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);
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end entity crc_core;
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architecture Behavioral of crc_core is
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begin
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crcOut(0) <= crcIn(2) xor crcIn(8) xor data(2);
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crcOut(1) <= crcIn(0) xor crcIn(3) xor crcIn(9) xor data(0) xor data(3);
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crcOut(2) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(10) xor data(0) xor data(1) xor data(4);
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crcOut(3) <= crcIn(1) xor crcIn(2) xor crcIn(5) xor crcIn(11) xor data(1) xor data(2) xor data(5);
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crcOut(4) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(6) xor crcIn(12) xor data(0) xor data(2) xor data(3) xor data(6);
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crcOut(5) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(7) xor crcIn(13) xor data(1) xor data(3) xor data(4) xor data(7);
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crcOut(6) <= crcIn(4) xor crcIn(5) xor crcIn(14) xor data(4) xor data(5);
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crcOut(7) <= crcIn(0) xor crcIn(5) xor crcIn(6) xor crcIn(15) xor data(0) xor data(5) xor data(6);
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crcOut(8) <= crcIn(1) xor crcIn(6) xor crcIn(7) xor crcIn(16) xor data(1) xor data(6) xor data(7);
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crcOut(9) <= crcIn(7) xor crcIn(17) xor data(7);
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crcOut(10) <= crcIn(2) xor crcIn(18) xor data(2);
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crcOut(11) <= crcIn(3) xor crcIn(19) xor data(3);
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crcOut(12) <= crcIn(0) xor crcIn(4) xor crcIn(20) xor data(0) xor data(4);
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crcOut(13) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(21) xor data(0) xor data(1) xor data(5);
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crcOut(14) <= crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(22) xor data(1) xor data(2) xor data(6);
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crcOut(15) <= crcIn(2) xor crcIn(3) xor crcIn(7) xor crcIn(23) xor data(2) xor data(3) xor data(7);
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crcOut(16) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(24) xor data(0) xor data(2) xor data(3) xor data(4);
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crcOut(17) <= crcIn(0) xor crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(25) xor data(0) xor data(1) xor data(3) xor data(4) xor data(5);
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crcOut(18) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(26) xor data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(6);
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crcOut(19) <= crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(27) xor data(1) xor data(2) xor data(3) xor data(5) xor data(6) xor data(7);
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crcOut(20) <= crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(28) xor data(3) xor data(4) xor data(6) xor data(7);
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crcOut(21) <= crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(29) xor data(2) xor data(4) xor data(5) xor data(7);
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crcOut(22) <= crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(30) xor data(2) xor data(3) xor data(5) xor data(6);
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crcOut(23) <= crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(31) xor data(3) xor data(4) xor data(6) xor data(7);
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crcOut(24) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor data(0) xor data(2) xor data(4) xor data(5) xor data(7);
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crcOut(25) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor data(0) xor data(1) xor data(2) xor data(3) xor data(5) xor data(6);
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crcOut(26) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(6) xor data(7);
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crcOut(27) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor data(1) xor data(3) xor data(4) xor data(5) xor data(7);
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crcOut(28) <= crcIn(0) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor data(0) xor data(4) xor data(5) xor data(6);
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crcOut(29) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor data(0) xor data(1) xor data(5) xor data(6) xor data(7);
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crcOut(30) <= crcIn(0) xor crcIn(1) xor crcIn(6) xor crcIn(7) xor data(0) xor data(1) xor data(6) xor data(7);
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crcOut(31) <= crcIn(1) xor crcIn(7) xor data(1) xor data(7);
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end architecture Behavioral;
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