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crc_Lösung

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allamaaki80515 2026-01-13 09:59:29 +01:00
parent 44296a640b
commit 8997e1cb97
1 changed files with 80 additions and 74 deletions
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154
hardware/signal_processing/crc.vhd
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@ -8,33 +8,36 @@ library work;
entity crc is entity crc is
port ( port (
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State; task_start : in std_logic;
signal_read : out std_logic; task_state : out work.task.State;
signal_readdata : in std_logic_vector(31 downto 0);
signal_write : out std_logic; signal_read : out std_logic;
signal_writedata: out std_logic_vector(31 downto 0) signal_readdata : in std_logic_vector( 31 downto 0 );
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
); );
end entity crc; end entity crc;
architecture rtl of crc is architecture rtl of crc is
signal current_task_state : work.task.State; signal current_task_state : work.task.State;
signal next_task_state : work.task.State; signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN := 0; signal index : integer range 0 to work.task.STREAM_LEN;
constant CRC_INIT : std_logic_vector(31 downto 0) := X"FFFFFFFF"; constant CRC_INIT : std_logic_vector(31 downto 0) := X"FFFFFFFF";
constant CRC_POLY : std_logic_vector(31 downto 0) := X"EDB88320"; constant CRC_POLY : std_logic_vector(31 downto 0) := X"EDB88320";
signal crc : std_logic_vector(31 downto 0) := CRC_INIT;
signal data_reg : std_logic_vector(31 downto 0); signal crc_reg : std_logic_vector(31 downto 0) := CRC_INIT;
signal data_valid : std_logic := '0'; signal data_reg : std_logic_vector(31 downto 0);
signal data_ready : std_logic := '0';
begin begin
task_state <= current_task_state; task_state <= current_task_state;
-- TASK STATE MACHINE (VORLAGE - nicht ändern!) task_state_transitions : process ( current_task_state, task_start, index ) is
task_state_transitions: process(current_task_state, task_start, index)
begin begin
next_task_state <= current_task_state; next_task_state <= current_task_state;
case current_task_state is case current_task_state is
@ -43,8 +46,7 @@ begin
next_task_state <= work.task.TASK_RUNNING; next_task_state <= work.task.TASK_RUNNING;
end if; end if;
when work.task.TASK_RUNNING => when work.task.TASK_RUNNING =>
-- WICHTIG: Schreiben nach 1024 Werten (index 0-1023) if index = work.task.STREAM_LEN then
if index = 1023 then
next_task_state <= work.task.TASK_DONE; next_task_state <= work.task.TASK_DONE;
end if; end if;
when work.task.TASK_DONE => when work.task.TASK_DONE =>
@ -54,67 +56,71 @@ begin
end case; end case;
end process; end process;
-- Data Channel Control
signal_read <= '1' when current_task_state = work.task.TASK_RUNNING signal_read <= '1' when current_task_state = work.task.TASK_RUNNING
and data_valid = '0' and data_ready = '0'
and index < 1024 and index < work.task.STREAM_LEN
else '0'; else '0';
signal_write <= '1' when current_task_state = work.task.TASK_DONE else '0'; signal_write <= '1' when current_task_state = work.task.TASK_DONE else '0';
signal_writedata <= crc xor X"FFFFFFFF"; -- Final XOR
signal_writedata <= crc_reg xor X"FFFFFFFF";
-- Haupt-Sync Process (identisch zur SW-Version) sync : process ( clk, reset ) is
sync: process(clk, reset) variable temp_crc : std_logic_vector(31 downto 0);
variable temp_crc : std_logic_vector(31 downto 0); begin
begin if reset = '1' then
if reset = '1' then current_task_state <= work.task.TASK_IDLE;
current_task_state <= work.task.TASK_IDLE; index <= 0;
index <= 0; crc_reg <= CRC_INIT;
crc <= CRC_INIT; data_reg <= X"00000000";
data_reg <= (others => '0'); data_ready <= '0';
data_valid <= '0';
elsif rising_edge(clk) then
elsif rising_edge(clk) then current_task_state <= next_task_state;
current_task_state <= next_task_state;
case next_task_state is
case next_task_state is when work.task.TASK_IDLE =>
when work.task.TASK_IDLE => index <= 0;
index <= 0; crc_reg <= CRC_INIT;
crc <= CRC_INIT; data_ready <= '0';
data_valid <= '0'; data_reg <= X"00000000";
when work.task.TASK_RUNNING =>
-- DATA LESEN (Timing korrekt)
if signal_read = '1' then
data_reg <= signal_readdata;
data_ready <= '1';
end if;
-- CRC UPDATE (INDEX PRÜFEN VOR Update!)
if data_ready = '1' then
-- WICHTIG: Index bleibt gleich bis TASK_DONE triggert!
--temp_crc := crc_reg xor data_reg; -- Berechne aber schreibe nicht sofort
when work.task.TASK_RUNNING => temp_crc := crc_reg xor data_reg;
-- 1. DATA LESEN (Timing: signal_read='1' -> NEXT CLK data_valid) for i in 0 to 31 loop
if signal_read = '1' then if temp_crc(0) = '1' then
data_reg <= signal_readdata; temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1)) xor CRC_POLY;
data_valid <= '1'; else
end if; temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1));
end if;
end loop;
-- 2. CRC UPDATE (zlib: XOR dann 32x bitweise LSB-first) crc_reg <= temp_crc;
if data_valid = '1' then data_ready <= '0';
temp_crc := crc xor data_reg;
crc <= temp_crc; -- INDEX NUR erhöhen wenn NICHT letzter!
if index < work.task.STREAM_LEN then
-- 32 Bit LSB-first Verarbeitung in EINEM Takt (wie SW)
for i in 0 to 31 loop
if temp_crc(0) = '1' then
temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1)) xor CRC_POLY;
else
temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1));
end if;
end loop;
crc <= temp_crc;
data_valid <= '0';
index <= index + 1; index <= index + 1;
end if; end if; -- Bei index=1023: bleibt 1023 → TASK_DONE triggert!
end if;
when work.task.TASK_DONE =>
index <= 0; when work.task.TASK_DONE =>
data_valid <= '0'; index <= 0;
end case; data_ready <= '0';
end if; end case;
end process; end if;
end process sync;
end architecture rtl; end architecture rtl;