From a980ef180eae87ead69c6dd216556f7b34953caf Mon Sep 17 00:00:00 2001 From: schoeffelbe82781 Date: Wed, 4 Dec 2024 09:37:28 +0100 Subject: [PATCH] Finished Task Rand in vhdl --- hardware/signal_processing/rand.vhd | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/hardware/signal_processing/rand.vhd b/hardware/signal_processing/rand.vhd index 4eb0fb9..b14a5a1 100644 --- a/hardware/signal_processing/rand.vhd +++ b/hardware/signal_processing/rand.vhd @@ -60,6 +60,9 @@ begin end process task_state_transitions; sync : process ( clk, reset ) is + variable var_lsfr_logic : std_logic_vector( 31 downto 0); + variable var_lsfr_signed : SIGNED( 31 downto 0); + begin if ( reset = '1' ) then current_task_state <= work.task.TASK_IDLE; @@ -85,21 +88,24 @@ begin case Calc_State is when CALC_IDLE => signal_write <= '0'; - lsfr_std_logic <= STD_LOGIC_VECTOR(lsfr); - if(lsfr_std_logic(0) = '1') then - lsfr <= SIGNED(lsfr_std_logic srl 1); - lsfr <= SIGNED(lsfr_std_logic XOR POLYNOM); + var_lsfr_logic := STD_LOGIC_VECTOR(lsfr); + if(var_lsfr_logic(0) = '1') then + var_lsfr_logic := '0' & (var_lsfr_logic(31 downto 1)); + --var_lsfr_logic := (var_lsfr_logic(31:1); + var_lsfr_logic := (var_lsfr_logic XOR POLYNOM); else - lsfr <= SIGNED(lsfr_std_logic srl 1); + --var_lsfr_logic := (var_lsfr_logic srl 1); + var_lsfr_logic := '0' & var_lsfr_logic(31 downto 1); end if; - lsfr <= SIGNED(lsfr_std_logic); - lsfr_dump <= lsfr; + var_lsfr_signed := SIGNED(var_lsfr_logic); + lsfr_dump <= SIGNED(var_lsfr_logic); - if(lsfr_std_logic(30) = '1') then - lsfr <= lsfr(31 downto 31) & "1000000" & lsfr(23 downto 0); + if(var_lsfr_signed(30) = '1') then + var_lsfr_signed := var_lsfr_signed(31 downto 31) & "1000000" & var_lsfr_signed(23 downto 0); else - lsfr <= lsfr(31 downto 31) & "011111" & lsfr(24 downto 0); + var_lsfr_signed := var_lsfr_signed(31 downto 31) & "011111" & var_lsfr_signed(24 downto 0); end if; + lsfr <= var_lsfr_signed; Calc_State <= CALC_WRITE; when CALC_WRITE => signal_write <= '1';