KutningJo/signal_processing_vorlage
2
0
Fork 19
Code Issues Pull Requests Releases Wiki Activity

Finished VHDL for Sine Task

Browse Source
This commit is contained in:
schoeffelbe82781 2024-11-20 10:02:38 +01:00
parent 151772a809
commit c7ee1a4da7
1 changed files with 62 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
hardware/signal_processing/sine.vhd
View File

@ -32,9 +32,11 @@ architecture rtl of sine is
type CalcState is ( type CalcState is (
CALC_IDLE, CALC_IDLE,
CALC_READ, CALC_ANGLE,
CALC_PROCESS, CALC_START,
CALC_WRITE CALC_BUSY,
CALC_WRITE,
CALC_DONE
); );
signal Calc_State : CalcState; signal Calc_State : CalcState;
@ -42,7 +44,9 @@ architecture rtl of sine is
signal busy_ipcore : std_logic; signal busy_ipcore : std_logic;
signal result_valid_ipcore : std_logic; signal result_valid_ipcore : std_logic;
signal phase_ipcore : signed(31 downto 0); signal angle_ipcore : signed(31 downto 0);
signal step_size_adapted : std_logic_vector( 31 downto 0 );
signal sine_amplitude : signed(31 downto 0);
signal sine_ipcore : signed(31 downto 0); signal sine_ipcore : signed(31 downto 0);
@ -59,7 +63,7 @@ begin
busy => busy_ipcore, busy => busy_ipcore,
result_valid => result_valid_ipcore, result_valid => result_valid_ipcore,
-- " TODO Check if this is allowed (direkt access to maped signal)" -- " TODO Check if this is allowed (direkt access to maped signal)"
angle => phase_ipcore, angle => angle_ipcore,
sine => sine_ipcore sine => sine_ipcore
); );
@ -72,7 +76,7 @@ begin
next_task_state <= work.task.TASK_RUNNING; next_task_state <= work.task.TASK_RUNNING;
end if; end if;
when work.task.TASK_RUNNING => when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then if ( index = work.task.STREAM_LEN ) then
next_task_state <= work.task.TASK_DONE; next_task_state <= work.task.TASK_DONE;
end if; end if;
when work.task.TASK_DONE => when work.task.TASK_DONE =>
@ -86,25 +90,66 @@ begin
begin begin
if ( reset = '1' ) then if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE; current_task_state <= work.task.TASK_IDLE;
Calc_State <= CALC_IDLE;
index <= 0; index <= 0;
signal_write <= '0';
elsif ( rising_edge( clk ) ) then elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state; current_task_state <= next_task_state;
case next_task_state is case next_task_state is
when work.task.TASK_IDLE => when work.task.TASK_IDLE =>
index <= 0; index <= 0;
signal_write <= '0'; signal_write <= '0';
when work.task.TASK_RUNNING => Calc_State <= CALC_IDLE;
index <= index + 1;
signal_write <= '1'; when work.task.TASK_RUNNING =>
signal_writedata <= ( others => '0' ); case Calc_State is
when work.task.TASK_DONE => when CALC_IDLE =>
index <= 0; angle_ipcore <= SIGNED(phase);
signal_write <= '0'; Calc_State <= CALC_START;
when CALC_ANGLE =>
angle_ipcore <= (angle_ipcore + (SIGNED(step_size_adapted)));
Calc_State <= CALC_START;
when CALC_START =>
data_valid_ipcore <= '1';
if(busy_ipcore = '1') then
Calc_State <= CALC_BUSY;
end if;
when CALC_BUSY =>
data_valid_ipcore <= '0';
if(result_valid_ipcore = '1') then
Calc_State <= CALC_WRITE;
end if;
when CALC_WRITE =>
-- sine_amplitude <= sine_ipcore(30 downto 23) + (signed(amplitude))(30 downto 23) - "127";
sine_amplitude <= sine_ipcore(31 downto 31) & (sine_ipcore(30 downto 23) + (signed(amplitude(30 downto 23)) - 127)) & sine_ipcore(22 downto 0);
-- sine_amplitude <= STD_LOGIC_VECTOR(sine_ipcore(30 downto 23)) + STD_LOGIC_VECTOR(amplitude(30 downto 23)) - "127";
signal_write <= '1';
Calc_State <= CALC_DONE;
when CALC_DONE =>
signal_write <= '0';
index <= index + 1;
Calc_State <= CALC_ANGLE;
end case;
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case; end case;
end if; end if;
end process sync; end process sync;
signal_writedata <= STD_LOGIC_VECTOR(sine_amplitude);
--step_size_adapted <= (step_size(31-5 downto 0) & "00000");
step_size_adapted <= (step_size );
task_state <= current_task_state; task_state <= current_task_state;
phase_ipcore <= (SIGNED(phase)); -- #TODO phase_ipcore <= (SIGNED(phase));
end architecture rtl; end architecture rtl;