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brandlfl78731 2024-11-20 11:32:11 +01:00
parent 03a4e64337
commit cfe1e2927c
9 changed files with 3016 additions and 2 deletions
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96
hardware/signal_processing/sine.vhd
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@ -26,11 +26,40 @@ end entity sine;
architecture rtl of sine is architecture rtl of sine is
signal current_task_state : work.task.State; signal current_task_state : work.task.State; --multiple sources
signal next_task_state : work.task.State; signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN; signal index : integer range 0 to work.task.STREAM_LEN; --multiple sources
--Selbst angelegte Signal:
signal data_valid_flag : std_logic;
signal busy_flag : std_logic;
signal result_valid_flag : std_logic;
signal angle_sig : signed( 31 downto 0);
signal ergebnis : signed( 31 downto 0 );
--Zustände für die Zustandsmaschine für die Berechnung
type CalcState is (
CALC_IDLE,
CALC_SINE,
CALC_STORE_RESULT
);
--Signale für die Zustandsmaschine für die Berechnung
signal current_calc_state : CalcState;
signal next_calc_state : CalcState;
begin begin
u_float_sine : entity work.float_sine -- Das hier ist der Core!
port map (
clk => clk,
reset => reset,
data_valid => data_valid_flag, --# load new input data
busy => busy_flag, --# generating new result
result_valid => result_valid_flag, --# flag when result is valid
angle => angle_sig, -- angle in brads (2**size brads = 2*pi radians)
sine => ergebnis --Hierzu nachfragen
);
--Bei diesem task nichts ändern!
task_state_transitions : process ( current_task_state, task_start, index ) is task_state_transitions : process ( current_task_state, task_start, index ) is
begin begin
next_task_state <= current_task_state; next_task_state <= current_task_state;
@ -50,6 +79,69 @@ begin
end case; end case;
end process task_state_transitions; end process task_state_transitions;
--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Fertig
calc_state_transitions: process (all) is
begin
next_calc_state <= current_calc_state;
case current_calc_state is
when CALC_IDLE=>
if (current_task_state= work.task.TASK_RUNNING) then
next_calc_state <= CALC_SINE;
end if;
when CALC_SINE =>
if (result_valid_flag = '1') then
next_calc_state <= CALC_STORE_RESULT;
end if;
when CALC_STORE_RESULT =>
next_calc_state <= CALC_IDLE;
end case;
end process calc_state_transitions;
--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks
task_sync : process (clk, reset) is
begin
if (reset = '1') then
current_task_state <= work.task.TASK_IDLE;
elsif (rising_edge( clk)) then
current_task_state <= next_task_state;
case next_task_state is
when work.task. TASK_IDLE => null;
when work.task. TASK_RUNNING => null;
when work.task. TASK_DONE => null;
end case;
end if;
end process task_sync;
--Zustandsspeicher und Ausgangsschaltnetz zu Berechnung
sync : process (clk, reset) is
begin
if (reset = '1') then
index <= 0;
current_calc_state <= CALC_IDLE;
ergebnis <= (others => '0');
signal_write <= '0';
elsif (rising_edge( clk)) then
current_calc_state <= next_calc_state;
case next_calc_state is
when CALC_IDLE =>
data_valid_flag <= '0';
signal_write <= '0';
when CALC_SINE => --hier Berechnung mit IP Core?
data_valid_flag <= '1';
when CALC_STORE_RESULT =>
data_valid_flag <= '0';
index <= index + 1;
signal_write <= '1';
signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core
end case;
end if;
end process sync;
task_state <= current_task_state;
--Altes Programm
sync : process ( clk, reset ) is sync : process ( clk, reset ) is
begin begin
if ( reset = '1' ) then if ( reset = '1' ) then

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