Versuch 2 Hardware funktioniert

hardware/signal_processing/sine.vhd

@@ -36,10 +36,12 @@ architecture rtl of sine is
 	signal result_valid_flag : std_logic;
 	signal angle_sig : signed( 31 downto 0);
 	signal ergebnis :  signed( 31 downto 0 );
+	signal ampl_sig : signed( 31 downto 0 );
 
 	--Zustände für die Zustandsmaschine für die Berechnung
 	type CalcState is (
 		CALC_IDLE,
+		CALC_START,
 		CALC_SINE,
 		CALC_STORE_RESULT
 	);
@@ -49,6 +51,9 @@ architecture rtl of sine is
 
 begin
     u_float_sine : entity work.float_sine -- Das hier ist der Core!
+	generic map (
+		ITERATIONS => 8
+	)
     port map (
         clk 	=> 		clk,
         reset 	=>		reset,
@@ -60,7 +65,7 @@ begin
     );
 
 	--Bei diesem task nichts ändern!
-    task_state_transitions : process ( current_task_state, task_start, index ) is
+    task_state_transitions : process ( all ) is
     begin
         next_task_state <= current_task_state;
         case current_task_state is
@@ -87,14 +92,20 @@ begin
 		case current_calc_state is
 			when CALC_IDLE=>
 				if (current_task_state= work.task.TASK_RUNNING) then 
-					next_calc_state <= CALC_SINE;
+					next_calc_state <= CALC_START;
 				end if;
+			when CALC_START=>
+				next_calc_state <= CALC_SINE;
 			when CALC_SINE =>
-				if (result_valid_flag = '1') then
+				if (result_valid_flag = '1' and busy_flag = '0') then 	--or falling_edge( busy) ?
 					next_calc_state <= CALC_STORE_RESULT;
 				end if;
 			when CALC_STORE_RESULT =>
+				if ( index = work.task.STREAM_LEN ) then
 					next_calc_state <= CALC_IDLE;
+				else
+					next_calc_state <= CALC_START;
+				end if;
 		end case;
 	end process calc_state_transitions;
 
@@ -120,50 +131,35 @@ begin
 	begin
 		if (reset = '1') then
 			index <= 0;
+			data_valid_flag <= '0';
 			current_calc_state <= CALC_IDLE;
-			ergebnis <= (others => '0'); 
+			--ergebnis <= (others => '0');  --Wird von IP Core gesteuert und darf deshalb hier nicht getrieben werden
+			signal_writedata <= (others => '0');
 			signal_write <= '0';
+			angle_sig <= (others => '0');
 		elsif (rising_edge( clk)) then
 			current_calc_state <= next_calc_state; 
 			case next_calc_state is 
 				when CALC_IDLE =>
 					data_valid_flag <= '0';
 					signal_write <= '0';
-				when CALC_SINE => 				--hier Berechnung mit IP Core?
+					angle_sig <= signed (phase);
+					ampl_sig <= signed (amplitude);
+				when CALC_START =>
 					data_valid_flag <= '1';
-				when CALC_STORE_RESULT =>
+					signal_write <= '0';
+					angle_sig <= angle_sig + signed(step_size); --step_size = 2 * PI / 32
+				when CALC_SINE => 				--hier Berechnung mit IP Core?
 					data_valid_flag <= '0';
+				when CALC_STORE_RESULT =>
 					index <= index + 1;
 					signal_write <= '1';
-					signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core
+					--Berechne float multiplikation zu Fuss. Exponent + Exponent usw.
+					signal_writedata <= std_logic_vector( ergebnis(31 downto 31) & (ergebnis(30 downto 23) + (signed(ampl_sig(30 downto 23)) - 127)) & ergebnis(22 downto 0));
+
 			end case;
 		end if;
 	end process sync;
 	task_state <= current_task_state;
 
---Altes Programm
-    sync : process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            current_task_state <= work.task.TASK_IDLE;
-            index <= 0;
-        elsif ( rising_edge( clk ) ) then
-            current_task_state <= next_task_state;
-            case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
-            when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
-            end case;
-        end if;
-    end process sync;
-
-    task_state <= current_task_state;
-
 end architecture rtl;

tests/hardware/task_cosine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 10:17:57 on Nov 27,2024
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "sine(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.cosine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.test_task_cosine(test)#1
+# Loading work.float(body)
+# Loading work.task_sine(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.cordic_pkg(body)
+# Loading work.sine(rtl)#1
+# Loading work.float_sine(rtl)#1
+# Loading work.fixed_sine(rtl)#1
+# Loading work.cordic(rtl)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 10:17:57 on Nov 27,2024, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 1

tests/hardware/task_cosine/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

tests/hardware/task_sine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_sine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 10:15:59 on Nov 27,2024
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "sine(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.sine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.test_task_sine(test)#1
+# Loading work.float(body)
+# Loading work.task_sine(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.cordic_pkg(body)
+# Loading work.sine(rtl)#1
+# Loading work.float_sine(rtl)#1
+# Loading work.fixed_sine(rtl)#1
+# Loading work.cordic(rtl)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 10:16:00 on Nov 27,2024, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 1