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1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
73c4f491fd |
@ -1,26 +1,13 @@
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------------------------------------------------------------------------
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-- fft
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--
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-- calculation of FFT magnitudes
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-- calculation of FFT magnitude
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--
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-- Inputs:
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-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
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--
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-- Outputs
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-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
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--
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--
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-- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor
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-- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist)
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-- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln
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-- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0)
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-- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich)
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-- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float)
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-- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32).
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-- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist)
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-- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html)
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-- (z.B: ein Array verwenden, um die Werte zu sortieren)
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-- Dann das Ergebnis in den Ausgangsfifo speichern
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--
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-----------------------------------------------------------------------
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library ieee;
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@ -32,130 +19,106 @@ library work;
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use work.task.all;
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use work.float.all;
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entity fft is
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generic (
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity fft;
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architecture rtl of fft is
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-- Signale für Task State Machine
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--signal index : integer range 0 to 2000;
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-- component des Verilog IP-Cores fuer die FFT
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component fftmain is
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port(
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clock: in std_logic; -- Master Clock
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reset: in std_logic; -- Active High Asynchronous Reset
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di_en: in std_logic; -- Input Data Enable
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di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
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di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
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do_en: out std_logic; -- Output Data Enable
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do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
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do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
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);
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end component;
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--own signals:
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--signal input_re : float(31 downto 0);
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-- Signale Input skaliert
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signal fft_float_input : signed( 31 downto 0 );
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signal fft_float_scaled_input : signed( 31 downto 0 );
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--use xxx.lib?; --componenteninstanziierung FFT IP-Core r22sdf
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--component foo is
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--generic (...)
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--port(...);
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--end component;
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-- Signale fuer FFT-IP Core
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-- fft data input signal
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signal fft_input_data_enable: std_logic;
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signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
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signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
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-- fft output data
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signal fft_output_valid : std_logic;
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signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
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signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
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component fftmain is
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generic (
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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di_en : in std_logic;
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di_re : in std_logic_vector(input_data_width-1 downto 0);
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di_im : in std_logic_vector(input_data_width-1 downto 0);
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do_en : in std_logic;
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do_re : in std_logic_vector(input_data_width-1 downto 0);
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do_im : in std_logic_vector(input_data_width-1 downto 0)
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--task_start : in std_logic;
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--task_state : out work.task.State;
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--signal_read : out std_logic;
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--signal_readdata : in std_logic_vector( 31 downto 0 );
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--signal_write : out std_logic;
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--signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end component fftmain;
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---State machine ----------------------------------
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TYPE State_type IS (A, B, C, D); -- Define the states
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SIGNAL State : State_Type; -- Create a signal that uses
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-- the different states
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-- Signale fuer Magnitude IP-Core
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signal fft_mag_calc_valid : std_logic;
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signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
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-- Signale fuer Ergebnis skaliert
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signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);
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signal fft_float_scaled : signed( 31 downto 0 );
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-- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
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signal data_memory : work.reg32.RegArray( 0 to 1023 );
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signal index_reversed : std_logic_vector(9 downto 0);
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signal index_output_sv : std_logic_vector(9 downto 0);
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signal index_output : integer range 0 to 1023;
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-- Signal um in den Write FIFO zu schreiben
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signal wr_fifo : std_logic;
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begin
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-----------------------------------------------------------------------------------------------
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-- Hier muss der Verilog FFT IP-Core instanziert werden
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-----------------------------------------------------------------------------------------------
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--u_fft : fftmain
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-- port map (
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-- clock => , -- system clock
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-- reset => , -- Active High Asynchronous Reset
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-- di_en => , -- Input Data Enable
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-- di_re => , -- Input Data (Real)
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-- di_im => , -- Input Data (Imag)
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-- do_en => , -- Output Data Enable
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-- do_re => , -- Output Data (Real)
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-- do_im => -- Output Data (Imag)
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-- );
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fft_output_valid <= '0';
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data_out_re <= (others => '0');
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data_out_im <= (others => '0');
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u_fft : fftmain
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port map (
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clock => clk,
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reset => fft_reset,
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-----------------------------------------------------------------------------------------------
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-- Hier muss der VHDL Magnitue IP-COre instanziert werden
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-----------------------------------------------------------------------------------------------
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-- u_fft_mag_calc : entity work.fft_magnitude_calc
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-- port map (
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-- clk => , -- system clock
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-- reset => , -- Active High Asynchronous Reset
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-- input_valid => , -- Input Data Valid
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-- input_re => , -- Input Realteil in Fixpoint format
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-- input_im => , -- Input Imaginaerteil in Fixpoint format
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-- output_valid => , -- Output Data Valid
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-- output_magnitude => -- Magnitude Output in Fixpoint format
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-- );
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di_en => fft_input_data_enable,
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di_re => diata_in_re,
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di_im => data_in_im,
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do_en => fft_output_valid,
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do_re => data_out_re,
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do_im => data_out_im
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);
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fft_mag_calc_valid <= '1' when index = 0 else '0';
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fft_mag_calc_result <= (others => '0');
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u_fft_mag_calc : entity work.fft_magnitude_calc
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port map (
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clk => clk,
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reset => reset,
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input_valid => fft_output_valid,
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input_re => data_out_re,
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input_im => data_out_im,
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output_valid => fft_mag_calc_valid,
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output_magnitude => fft_mag_calc_result
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);
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-----------------------------------------------------------------------------------------------
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-- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
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-----------------------------------------------------------------------------------------------
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task_state_transitions : process (all) is
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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@ -164,7 +127,7 @@ begin
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = 2 ) then
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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@ -174,157 +137,28 @@ begin
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end case;
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end process task_state_transitions;
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-----------------------------------------------------------------------------------------------
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-- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
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-----------------------------------------------------------------------------------------------
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-- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
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-----------------------------------------------------------------------------------------------
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-- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
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-----------------------------------------------------------------------------------------------
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sync : process ( clk, reset ) is
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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wr_fifo <= '0';
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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wr_fifo <= '0';
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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when work.task.TASK_RUNNING =>
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-- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
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-- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
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if ( index_output = work.task.STREAM_LEN - 1 ) then
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index <= index + 1;
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end if;
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if index = 1 then
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wr_fifo <= '1';
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end if;
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when work.task.TASK_DONE => null;
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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end process sync;
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-----------------------------------------------------------------------------------------------
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--
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-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
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-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
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-- und im naechsten Takt schon weiter verarbeitet werden können
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--
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-- Erforderliches Scaling:
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--
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-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
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-- multiplication is a simple addition of the exponents.
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-- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
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-- This means an divsion through 16 -> exponent needs an addition of - 4
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--
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-- fft_float_input = gelesener Wert vom FIFO (floating point)
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-- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
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-- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
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-----------------------------------------------------------------------------------------------
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fft_float_input <= signed(signal_readdata);
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fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden
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-----------------------------------------------------------------------------------------------
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--
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-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
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-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
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-- und im naechsten Takt schon weiter verarbeitet werden können
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--
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-- Erforderliches Scaling:
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--
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-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
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-- multiplication is a simple addition of the exponents.
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-- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16
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-- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
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-- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
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-- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
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--
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-- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
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-- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
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-----------------------------------------------------------------------------------------------
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data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
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fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
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-----------------------------------------------------------------------------------------------
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-- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
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-- Umordnung der Ausgangswerte erfolgen
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--
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-- index_output_sv = std_logic_vector des Integer Ausgangsindex
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-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
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--
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c_index_output_sv:
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index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
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c_reversed_index:
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index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
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-----------------------------------------------------------------------------------------------
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-- Prozess steuert das hochzaehlen des Ausgang Index
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-----------------------------------------------------------------------------------------------
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p_number_output_sample: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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index_output <= 0;
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elsif ( rising_edge( clk ) ) then
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-- Ruecksetz Bedingung für index_output
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if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
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index_output <= 0;
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-- index_output hochzaehlen um in natural order im array zu speichern
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elsif fft_mag_calc_valid = '1' then
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index_output <= index_output + 1;
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-- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
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elsif wr_fifo = '1' then
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index_output <= index_output + 1;
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end if;
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end if;
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end process p_number_output_sample;
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-----------------------------------------------------------------------------------------------
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-- Prozess speichert das skalierte Endergbenis iun der natural order
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-----------------------------------------------------------------------------------------------
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p_output2float_memory: process ( clk, reset) is
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begin
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if ( reset = '1' ) then
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null;
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elsif ( rising_edge( clk ) ) then
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if fft_mag_calc_valid = '1' then
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data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
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end if;
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end if;
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end process p_output2float_memory;
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-----------------------------------------------------------------------------------------------
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-- Schreiben der berechneten Werte in den FIFO
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-----------------------------------------------------------------------------------------------
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p_output_fifo: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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signal_writedata <= (others => '0');
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signal_write <= '0';
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elsif ( rising_edge( clk ) ) then
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signal_write <= '0';
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if wr_fifo = '1' then
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signal_writedata <= data_memory(index_output);
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signal_write <= '1';
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end if;
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end if;
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end process p_output_fifo;
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-- Hier sollen die sonstigen benoetigten Anweisungen stehen
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task_state <= current_task_state;
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task_state <= current_task_state;
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end architecture rtl;
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@ -15,9 +15,9 @@ entity sine is
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task_start : in std_logic;
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task_state : out work.task.State;
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step_size : in work.reg32.word;
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phase : in work.reg32.word;
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amplitude : in work.reg32.word;
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step_size : in work.reg32.word; --Parameter, übergeben aus task_sine
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phase : in work.reg32.word; --Parameter, übergeben aus task_sine
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amplitude : in work.reg32.word; --Parameter, übergeben aus task_sine
|
||||
|
||||
signal_write : out std_logic;
|
||||
signal_writedata : out std_logic_vector( 31 downto 0 )
|
||||
@ -29,8 +29,139 @@ architecture rtl of sine is
|
||||
signal current_task_state : work.task.State;
|
||||
signal next_task_state : work.task.State;
|
||||
signal index : integer range 0 to work.task.STREAM_LEN;
|
||||
--own signals:
|
||||
signal data_valid : std_logic;
|
||||
signal busy : std_logic;
|
||||
signal angle : signed(31 downto 0);
|
||||
signal result_valid : std_logic;
|
||||
signal sine_value : signed(31 downto 0);
|
||||
|
||||
|
||||
signal output_value : signed(31 downto 0);
|
||||
|
||||
signal output_flag : std_logic;
|
||||
--signal exp : signed(7 downto 0);
|
||||
--signal tmp : signed(7 downto 0);
|
||||
|
||||
|
||||
---State machine ----------------------------------
|
||||
TYPE State_type IS (A, B, C, D); -- Define the states
|
||||
SIGNAL State : State_Type; -- Create a signal that uses
|
||||
-- the different states
|
||||
|
||||
|
||||
begin
|
||||
|
||||
u_float_sine : entity work.float_sine
|
||||
generic map (
|
||||
ITERATIONS => 8
|
||||
)
|
||||
port map(
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
data_valid => data_valid,
|
||||
angle => angle,
|
||||
busy => busy,
|
||||
result_valid => result_valid,
|
||||
sine => sine_value
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PROCESS (clk, reset)
|
||||
BEGIN
|
||||
If (reset = '1') THEN --RESET: State to A
|
||||
data_valid <= '0';
|
||||
output_flag <= '0';
|
||||
angle <= x"00000000";--x"1FFFFFFF";
|
||||
State <= A;
|
||||
|
||||
ELSIF rising_edge(clk) THEN -- if there is a rising edge of the
|
||||
-- clock, then do the stuff below
|
||||
|
||||
-- The CASE statement checks the value of the State variable,
|
||||
-- and based on the value and any other control signals, changes
|
||||
-- to a new state.
|
||||
CASE State IS
|
||||
|
||||
-- If the current state is A and P is set to 1, then the
|
||||
-- next state is B
|
||||
WHEN A => --set data_valid to 1 for one clock cycle
|
||||
IF index = 0 THEN
|
||||
angle <= signed(phase);
|
||||
|
||||
ELSE
|
||||
|
||||
|
||||
--angle <= angle;--x"1FFFFFFF"; --debug: 1,5 --> should result in sin() = 1
|
||||
END IF;
|
||||
|
||||
IF data_valid ='0' AND current_task_state = TASK_RUNNING THEN
|
||||
|
||||
data_valid <= '1';
|
||||
State <= B;
|
||||
END IF;
|
||||
|
||||
-- If the current state is B and P is set to 1, then the
|
||||
-- next state is C
|
||||
WHEN B =>
|
||||
IF data_valid ='1' THEN
|
||||
data_valid <= '0';
|
||||
State <= C;
|
||||
END IF;
|
||||
|
||||
|
||||
-- If the current state is C and P is set to 1, then the
|
||||
-- next state is D
|
||||
WHEN C =>
|
||||
IF result_valid = '1' AND busy = '0' THEN
|
||||
--sine_value <= sine;
|
||||
output_flag <= '1';
|
||||
data_valid <= '0';
|
||||
angle <= angle + signed(step_size); --winkel neu zuweisen
|
||||
State <= D;
|
||||
END IF;
|
||||
|
||||
-- If the current state is D and P is set to 1, then the
|
||||
-- next state is B.
|
||||
-- If the current state is D and P is set to 0, then the
|
||||
-- next state is A.
|
||||
WHEN D=>
|
||||
IF data_valid = '0' THEN
|
||||
output_flag <= '0';
|
||||
State <= A;
|
||||
--ELSE
|
||||
--State <= A;
|
||||
END IF;
|
||||
--WHEN others =>
|
||||
--State <= A;
|
||||
END CASE;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--end of state machine______________________________________
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--do not change
|
||||
|
||||
task_state_transitions : process ( current_task_state, task_start, index ) is
|
||||
begin
|
||||
next_task_state <= current_task_state;
|
||||
@ -40,17 +171,20 @@ begin
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
when work.task.TASK_RUNNING =>
|
||||
if ( index = work.task.STREAM_LEN - 1 ) then
|
||||
if ( index = work.task.STREAM_LEN ) then -- changed from index = work.task.STREAM_LEN - 1
|
||||
next_task_state <= work.task.TASK_DONE;
|
||||
end if;
|
||||
when work.task.TASK_DONE =>
|
||||
if ( task_start = '1' ) then
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
|
||||
end if;
|
||||
end case;
|
||||
end process task_state_transitions;
|
||||
--end of no not change
|
||||
|
||||
sync : process ( clk, reset ) is
|
||||
|
||||
sync : process ( clk, reset , signal_writedata) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
current_task_state <= work.task.TASK_IDLE;
|
||||
@ -61,17 +195,37 @@ begin
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
|
||||
|
||||
|
||||
when work.task.TASK_RUNNING =>
|
||||
index <= index + 1;
|
||||
signal_write <= '1';
|
||||
signal_writedata <= ( others => '0' );
|
||||
|
||||
--output:
|
||||
IF output_flag = '1' THEN
|
||||
index <= index + 1;
|
||||
signal_write <= '1';
|
||||
output_value <= sine_value;
|
||||
|
||||
output_value(30 downto 23) <= sine_value(30 downto 23) + (signed(amplitude(30 downto 23)) - 127); --change from +2 to correct exponent
|
||||
--wenn 1: +0, wenn 2: +1, wenn 4:2, wenn 8: 3 = Bit
|
||||
|
||||
|
||||
ELSE
|
||||
signal_write <= '0';
|
||||
END IF;
|
||||
|
||||
--signal_writedata <= std_logic_vector(to_unsigned(2, signal_writedata'length)); --test
|
||||
when work.task.TASK_DONE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
signal_write <= '0';
|
||||
|
||||
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process sync;
|
||||
|
||||
task_state <= current_task_state;
|
||||
signal_writedata <= std_logic_vector(output_value);--x"40800000";--( others => '0' );
|
||||
|
||||
end architecture rtl;
|
||||
|
||||
@ -2,9 +2,72 @@
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
|
||||
#include <math.h>
|
||||
#include <stdio.h>
|
||||
|
||||
typedef struct {
|
||||
float value;
|
||||
} Result;
|
||||
|
||||
|
||||
void generateSinusCurve(float samples_per_period, float phase, float amplitude, Result res[]) {
|
||||
float delta_phase = 2.0 * M_PI / samples_per_period;
|
||||
float current_phase = phase;
|
||||
|
||||
for (int i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
|
||||
res[i].value = amplitude * sinf(current_phase);
|
||||
current_phase += delta_phase;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
int task_sine_run( void * data ) {
|
||||
|
||||
// TODO
|
||||
|
||||
sine_config * task = (sine_config *) data;
|
||||
uint32_t data_channel_base = task -> base.sink;
|
||||
data_channel_clear( data_channel_base );
|
||||
float_word res;
|
||||
|
||||
|
||||
|
||||
|
||||
//float samples_per_period = 32.0;
|
||||
float samples_per_period = task ->samples_per_periode;
|
||||
float phase = task-> phase;
|
||||
float amplitude = task -> amplitude;
|
||||
|
||||
Result results[DATA_CHANNEL_DEPTH];
|
||||
|
||||
generateSinusCurve(samples_per_period, phase, amplitude, results);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
for (int i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
|
||||
//printf("Wert %d: %f\n", i, results[i].value);
|
||||
res.value = results[i].value;
|
||||
data_channel_write( data_channel_base, res.word);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -24,7 +24,7 @@ sine_config SINE_CONFIG = {
|
||||
.sink = DATA_CHANNEL_0_BASE,
|
||||
.cycle_count = 0 },
|
||||
.samples_per_periode = 32,
|
||||
.phase = 0.0,
|
||||
.phase = 0,
|
||||
.amplitude = 4.0 };
|
||||
|
||||
sine_config COSINE_CONFIG = {
|
||||
|
||||
@ -25,8 +25,8 @@ assert_level := error
|
||||
.PHONY: sim clean
|
||||
|
||||
sim: ${verilog_objs} ${vhdl_objs}
|
||||
@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -voptargs=+acc -c work.${main} -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" \
|
||||
| ../../scripts/highlight_test_results.sh
|
||||
@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -voptargs=+acc -c work.${main} -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all"
|
||||
#| ../../scripts/highlight_test_results.sh
|
||||
|
||||
gui: ${verilog_objs} ${vhdl_objs}
|
||||
@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -gGUI_MODE=true -voptargs=+acc work.${main} -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all"
|
||||
|
||||
@ -10,10 +10,9 @@ verilog_srcs = \
|
||||
|
||||
vhdl_srcs = \
|
||||
../../../hardware/system/reg32.vhd \
|
||||
../../../hardware/system/avalon_slave.vhd \
|
||||
../test_utility.vhd \
|
||||
../test_avalon_slave.vhd \
|
||||
../../hardware/test_data_channel.vhd \
|
||||
../../../hardware/system/avalon_slave.vhd \
|
||||
../../../hardware/system/avalon_slave_transitions.vhd \
|
||||
../../../hardware/system/task.vhd \
|
||||
../../../hardware/system/hardware_task_control.vhd \
|
||||
@ -26,6 +25,7 @@ vhdl_srcs = \
|
||||
../test_utility.vhd \
|
||||
../test_avalon_slave.vhd \
|
||||
../test_hardware_task.vhd \
|
||||
../../hardware/test_data_channel.vhd \
|
||||
../../data/add_rand.vhd \
|
||||
../../data/sine.vhd \
|
||||
../../data/fft.vhd \
|
||||
|
||||
@ -63,7 +63,7 @@ architecture test of test_task_fft is
|
||||
variable writedata_float : float32;
|
||||
variable writedata_real : real;
|
||||
variable expected_real : real;
|
||||
variable abs_err : real := 0.6;
|
||||
variable abs_err : real := 0.5e-1;
|
||||
variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
|
||||
variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
|
||||
file data_file : text;
|
||||
@ -110,13 +110,11 @@ architecture test of test_task_fft is
|
||||
std.textio.write( data_file_fft, "]" & LF );
|
||||
file_close( data_file_fft );
|
||||
|
||||
index := 0;
|
||||
while index < STREAM_LEN loop
|
||||
writedata_float := to_float( result( index ) );
|
||||
writedata_real := to_real( writedata_float );
|
||||
expected_real := work.fft_data.expected( index );
|
||||
assert_near( writedata_real, expected_real, abs_err );
|
||||
index := index + 1;
|
||||
end loop;
|
||||
|
||||
file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );
|
||||
|
||||
@ -1,2 +1 @@
|
||||
add wave -position end sim:/test_task_fft/dut/*
|
||||
add wave -position end sim:/test_task_fft/dut/u_fft/*
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user