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schmidtsv99309
7dd0ffc130 Fertig 2024-12-18 10:56:27 +01:00
10 changed files with 434 additions and 374 deletions
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113
hardware/signal_processing/add.vhd
View File

@ -30,7 +30,35 @@ architecture rtl of add is
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
signal float_add_start : std_logic := '0';
signal float_add_done : std_logic;
signal float_add_a : std_logic_vector(31 downto 0);
signal float_add_b : std_logic_vector(31 downto 0);
signal float_add_sum : std_logic_vector(31 downto 0) := (others => '0');
type CalcState is (
CALC_IDLE,
CALC_ADD,
CALC_STORE_RESULT
);
signal current_calc_state : CalcState;
signal next_calc_state : CalcState;
begin
u_float_add : entity work.float_add
port map(
clk => clk,
reset => reset,
start => float_add_start,
done => float_add_done,
A => float_add_a,
B => float_add_b,
sum => float_add_sum
);
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
@ -50,28 +78,85 @@ begin
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
calc_state_transistions : process (current_calc_state, current_task_state, float_add_done) is
begin
next_calc_state <= current_calc_state;
case current_calc_state is
when CALC_IDLE =>
if current_task_state = work.task.TASK_RUNNING then
next_calc_state <= CALC_ADD;
end if;
when CALC_ADD =>
if (float_add_done = '1') then
next_calc_state <= CALC_STORE_RESULT;
end if;
when CALC_STORE_RESULT =>
next_calc_state <= CALC_IDLE;
end case;
end process calc_state_transistions;
-- Synchronisation: Task-State
task_sync : process (clk, reset) is
begin
if ( reset = '1' ) then
if (reset = '1') then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
signal_write <= '0';
signal_writedata <= (others => '0');
elsif (rising_edge(clk)) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
if current_task_state = work.task.TASK_RUNNING then
-- Vorbereitung auf neue Berechnung
if index > 0 then
signal_a_read <= '1';
signal_b_read <= '1';
end if;--index <= index + 1;
else
signal_a_read <= '0';
signal_b_read <= '0';
--index <= 0;
end if;
if current_calc_state = CALC_STORE_RESULT then
signal_a_read <= '0';
signal_b_read <= '0';
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_writedata <= float_add_sum;
index <= index + 1;
else
signal_write <= '0';
end if;
end if;
end process task_sync;
-- Synchronisation: Calc-State
calc_sync : process (clk, reset) is
begin
if (reset = '1') then
current_calc_state <= CALC_IDLE;
float_add_start <= '0';
float_add_a <= (others => '0');
float_add_b <= (others => '0');
elsif (rising_edge(clk)) then
current_calc_state <= next_calc_state;
case current_calc_state is
when CALC_IDLE =>
float_add_start <= '0';
when CALC_ADD =>
float_add_a <= signal_a_readdata;
float_add_b <= signal_b_readdata;
float_add_start <= '1';
when CALC_STORE_RESULT =>
float_add_start <= '0';
end case;
end if;
end process sync;
end process calc_sync;
task_state <= current_task_state;
end architecture rtl;

273
hardware/signal_processing/fft.vhd
View File

@ -1,26 +1,13 @@
------------------------------------------------------------------------
-- fft
--
-- calculation of FFT magnitudes
-- calculation of FFT magnitude
--
-- Inputs:
-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
--
-- Outputs
-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
--
--
-- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor
-- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist)
-- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln
-- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0)
-- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich)
-- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float)
-- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32).
-- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist)
-- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html)
-- (z.B: ein Array verwenden, um die Werte zu sortieren)
-- Dann das Ergebnis in den Ausgangsfifo speichern
--
-----------------------------------------------------------------------
library ieee;
@ -35,10 +22,10 @@ library work;
entity fft is
generic (
-- input data width of real/img part
-- input data width of real/img part
input_data_width : integer := 32;
-- output data width of real/img part
-- output data width of real/img part
output_data_width : integer := 32
);
@ -48,10 +35,10 @@ entity fft is
task_start : in std_logic;
task_state : out work.task.State;
signal_read : out std_logic;
signal_readdata : in std_logic_vector( 31 downto 0 );
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
@ -59,103 +46,12 @@ end entity fft;
architecture rtl of fft is
-- Signale für Task State Machine
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
--signal index : integer range 0 to 2000;
-- component des Verilog IP-Cores fuer die FFT
component fftmain is
port(
clock: in std_logic; -- Master Clock
reset: in std_logic; -- Active High Asynchronous Reset
di_en: in std_logic; -- Input Data Enable
di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
do_en: out std_logic; -- Output Data Enable
do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
);
end component;
-- Signale Input skaliert
signal fft_float_input : signed( 31 downto 0 );
signal fft_float_scaled_input : signed( 31 downto 0 );
-- Signale fuer FFT-IP Core
-- fft data input signal
signal fft_input_data_enable: std_logic;
signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
-- fft output data
signal fft_output_valid : std_logic;
signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
-- Signale fuer Magnitude IP-Core
signal fft_mag_calc_valid : std_logic;
signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
-- Signale fuer Ergebnis skaliert
signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);
signal fft_float_scaled : signed( 31 downto 0 );
-- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
signal data_memory : work.reg32.RegArray( 0 to 1023 );
signal index_reversed : std_logic_vector(9 downto 0);
signal index_output_sv : std_logic_vector(9 downto 0);
signal index_output : integer range 0 to 1023;
-- Signal um in den Write FIFO zu schreiben
signal wr_fifo : std_logic;
begin
-----------------------------------------------------------------------------------------------
-- Hier muss der Verilog FFT IP-Core instanziert werden
-----------------------------------------------------------------------------------------------
--u_fft : fftmain
-- port map (
-- clock => , -- system clock
-- reset => , -- Active High Asynchronous Reset
-- di_en => , -- Input Data Enable
-- di_re => , -- Input Data (Real)
-- di_im => , -- Input Data (Imag)
-- do_en => , -- Output Data Enable
-- do_re => , -- Output Data (Real)
-- do_im => -- Output Data (Imag)
-- );
fft_output_valid <= '0';
data_out_re <= (others => '0');
data_out_im <= (others => '0');
-----------------------------------------------------------------------------------------------
-- Hier muss der VHDL Magnitue IP-COre instanziert werden
-----------------------------------------------------------------------------------------------
-- u_fft_mag_calc : entity work.fft_magnitude_calc
-- port map (
-- clk => , -- system clock
-- reset => , -- Active High Asynchronous Reset
-- input_valid => , -- Input Data Valid
-- input_re => , -- Input Realteil in Fixpoint format
-- input_im => , -- Input Imaginaerteil in Fixpoint format
-- output_valid => , -- Output Data Valid
-- output_magnitude => -- Magnitude Output in Fixpoint format
-- );
fft_mag_calc_valid <= '1' when index = 0 else '0';
fft_mag_calc_result <= (others => '0');
-----------------------------------------------------------------------------------------------
-- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
-----------------------------------------------------------------------------------------------
task_state_transitions : process (all) is
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
@ -164,7 +60,7 @@ begin
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = 2 ) then
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
@ -174,157 +70,28 @@ begin
end case;
end process task_state_transitions;
-----------------------------------------------------------------------------------------------
-- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
-----------------------------------------------------------------------------------------------
-- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
-----------------------------------------------------------------------------------------------
-- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
-----------------------------------------------------------------------------------------------
sync : process ( clk, reset ) is
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
wr_fifo <= '0';
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
wr_fifo <= '0';
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
when work.task.TASK_RUNNING =>
-- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
-- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
if ( index_output = work.task.STREAM_LEN - 1 ) then
index <= index + 1;
end if;
if index = 1 then
wr_fifo <= '1';
end if;
when work.task.TASK_DONE => null;
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
end process sync;
-----------------------------------------------------------------------------------------------
--
-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
-- und im naechsten Takt schon weiter verarbeitet werden können
--
-- Erforderliches Scaling:
--
-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
-- multiplication is a simple addition of the exponents.
-- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
-- This means an divsion through 16 -> exponent needs an addition of - 4
--
-- fft_float_input = gelesener Wert vom FIFO (floating point)
-- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
-- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
-----------------------------------------------------------------------------------------------
fft_float_input <= signed(signal_readdata);
fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden
-----------------------------------------------------------------------------------------------
--
-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
-- und im naechsten Takt schon weiter verarbeitet werden können
--
-- Erforderliches Scaling:
--
-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
-- multiplication is a simple addition of the exponents.
-- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16
-- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
-- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
-- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
--
-- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
-- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
-----------------------------------------------------------------------------------------------
data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
-----------------------------------------------------------------------------------------------
-- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
-- Umordnung der Ausgangswerte erfolgen
--
-- index_output_sv = std_logic_vector des Integer Ausgangsindex
-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
--
c_index_output_sv:
index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
c_reversed_index:
index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
-----------------------------------------------------------------------------------------------
-- Prozess steuert das hochzaehlen des Ausgang Index
-----------------------------------------------------------------------------------------------
p_number_output_sample: process ( clk, reset ) is
begin
if ( reset = '1' ) then
index_output <= 0;
elsif ( rising_edge( clk ) ) then
-- Ruecksetz Bedingung für index_output
if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
index_output <= 0;
-- index_output hochzaehlen um in natural order im array zu speichern
elsif fft_mag_calc_valid = '1' then
index_output <= index_output + 1;
-- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
elsif wr_fifo = '1' then
index_output <= index_output + 1;
end if;
end if;
end process p_number_output_sample;
-----------------------------------------------------------------------------------------------
-- Prozess speichert das skalierte Endergbenis iun der natural order
-----------------------------------------------------------------------------------------------
p_output2float_memory: process ( clk, reset) is
begin
if ( reset = '1' ) then
null;
elsif ( rising_edge( clk ) ) then
if fft_mag_calc_valid = '1' then
data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
end if;
end if;
end process p_output2float_memory;
-----------------------------------------------------------------------------------------------
-- Schreiben der berechneten Werte in den FIFO
-----------------------------------------------------------------------------------------------
p_output_fifo: process ( clk, reset ) is
begin
if ( reset = '1' ) then
signal_writedata <= (others => '0');
signal_write <= '0';
elsif ( rising_edge( clk ) ) then
signal_write <= '0';
if wr_fifo = '1' then
signal_writedata <= data_memory(index_output);
signal_write <= '1';
end if;
end if;
end process p_output_fifo;
-- Hier sollen die sonstigen benoetigten Anweisungen stehen
task_state <= current_task_state;
task_state <= current_task_state;
end architecture rtl;

187
hardware/signal_processing/rand.vhd
View File

@ -1,73 +1,114 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.task.all;
entity rand is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
seed : in work.reg32.word;
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity rand;
architecture rtl of rand is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.task.all;
entity rand is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
seed : in work.reg32.word;
signal_write : out std_logic;
signal_writedata : out std_logic_vector(31 downto 0)
);
end entity rand;
architecture rtl of rand is
signal lfsr_reg : std_logic_vector(31 downto 0);
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process(current_task_state, task_start, index) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if (task_start = '1') then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if (index = work.task.STREAM_LEN - 1) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if (task_start = '1') then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process(clk, reset) is
variable random_value : std_logic_vector(31 downto 0);
variable lfsr_feedback : std_logic;
begin
if (reset = '1') then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
lfsr_reg <= seed;
signal_write <= '0';
elsif (rising_edge(clk)) then
lfsr_feedback := lfsr_reg(31) xor lfsr_reg(21) xor lfsr_reg(1) xor lfsr_reg(0);
--lfsr_reg <= lfsr_feedback & lfsr_reg(31 downto 1);
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
lfsr_reg <= seed;
when work.task.TASK_RUNNING =>
lfsr_reg <= lfsr_feedback & lfsr_reg(31 downto 1);
random_value := lfsr_reg;
if random_value(30) = '1' then
random_value(29 downto 24) := "000000"; -- Exponent 129 (2^3)
--random_value(6 downto 1) := (others => '0');
random_value(23) := lfsr_reg(7);
end if;
if random_value(30) = '0' then
random_value(29 downto 25) := "11111"; -- Exponent 123 (2^-3)
--random_value(6 downto 2) := (others => '1');
random_value(24 downto 23) := lfsr_reg(5 downto 4);
end if;
random_value(31) := lfsr_reg(14);
signal_write <= '1';
signal_writedata <= random_value;
--lfsr_reg <= lfsr_feedback & lfsr_reg(31 downto 1);
index <= index + 1;
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;

137
hardware/signal_processing/sine.vhd
View File

@ -30,8 +30,49 @@ architecture rtl of sine is
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal valid_gen : std_logic;
signal angle_gen : signed(31 downto 0);
signal busy_gen : std_logic;
signal result_valid_gen : std_logic;
signal sine_gen : signed(31 downto 0);
signal sine_sign : std_logic; -- Vorzeichen
signal sine_exponent : signed(7 downto 0); -- Exponent
signal sine_mantissa : std_logic_vector(22 downto 0); -- Mantisse
signal scaled_exponent : signed(7 downto 0); -- Skalierter Exponent
signal scaled_sine : std_logic_vector(31 downto 0); -- Ergebnis
type CalcState is (
CALC_IDLE,
CALC_GEN,
CALC_WAIT,
CALC_STORE,
CALC_STORE_RESULT
);
signal current_calc_state : CalcState;
signal next_calc_state : CalcState;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
u_float_sine : entity work.float_sine
generic map (
ITERATIONS => 8
)
port map (
clk => clk,
reset => reset,
data_valid => valid_gen,
angle => angle_gen,
busy => busy_gen,
result_valid => result_valid_gen,
sine => sine_gen
);
task_state_transitions : process ( all ) is
begin
next_task_state <= current_task_state;
case current_task_state is
@ -50,28 +91,96 @@ begin
end case;
end process task_state_transitions;
calc_state_transistions : process ( all ) is
begin
next_calc_state <= current_calc_state;
case current_calc_state is
when CALC_IDLE =>
if current_task_state = work.task.TASK_RUNNING then
next_calc_state <= CALC_GEN;
end if;
when CALC_GEN =>
next_calc_state <= CALC_WAIT;
when CALC_WAIT =>
next_calc_state <= CALC_STORE;
when CALC_STORE =>
if result_valid_gen = '1' and busy_gen = '0' then
next_calc_state <= CALC_STORE_RESULT;
else
next_calc_state <= CALC_STORE;
end if;
when CALC_STORE_RESULT =>
next_calc_state <= CALC_IDLE;
end case;
end process calc_state_transistions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
if current_task_state = work.task.TASK_RUNNING then
end if;
if current_calc_state = CALC_STORE_RESULT then
index <= index + 1;
end if;
end if;
end process sync;
sine_sign <= sine_gen(31);
sine_exponent <= signed(sine_gen(30 downto 23));
sine_mantissa <= std_logic_vector(sine_gen(22 downto 0));
scaled_exponent <= sine_exponent + (signed(amplitude(30 downto 23)) - 127);
scaled_sine <= sine_sign & std_logic_vector(scaled_exponent) & sine_mantissa;
calc_sync : process ( clk, reset ) is
begin
if (reset = '1') then
current_calc_state <= CALC_IDLE;
valid_gen <= '0';
angle_gen <= (others => '0');
signal_write <= '0';
signal_writedata <= (others => '0');
elsif (rising_edge(clk)) then
current_calc_state <= next_calc_state;
signal_write <= '0';
case current_calc_state is
when CALC_IDLE =>
valid_gen <= '0';
if current_task_state = work.task.TASK_IDLE then
angle_gen <= signed(phase);
end if;
when CALC_GEN =>
if next_calc_state = CALC_WAIT then
valid_gen <= '1';
angle_gen <= angle_gen + signed(step_size);
end if;
when CALC_WAIT =>
valid_gen <= '0';
when CALC_STORE =>
null;
when CALC_STORE_RESULT =>
signal_write <= '1';
signal_writedata <= scaled_sine;
end case;
end if;
end process calc_sync;
task_state <= current_task_state;
end architecture rtl;

12
software/signal_processing/add.c
View File

@ -4,7 +4,17 @@
int task_add_run( void * task ) {
// TODO
add_config * config = ( add_config * ) task;
for ( uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++ ) {
float a;
float b;
data_channel_read( config-> sources[ 0 ], (uint32_t * ) & a);
data_channel_read( config-> sources[ 1 ], (uint32_t * ) & b);
float_word c;
c.value = a+b;
data_channel_write( config->sink, c.word );
}
return 0;
}

57
software/signal_processing/rand.c
View File

@ -1,12 +1,45 @@
#include "system/task_rand.h"
#include "system/hardware_task.h"
#include "system/data_channel.h"
#include "system/float_word.h"
int task_rand_run( void * task ) {
// TODO
return 0;
}
#include "system/task_rand.h"
#include "system/hardware_task.h"
#include "system/data_channel.h"
#include "system/float_word.h"
#include <stdio.h>
#include <system.h>
int task_rand_run(void *task) {
rand_config *config = (rand_config *)task;
uint32_t data_channel_base = DATA_CHANNEL_2_BASE;
uint32_t lfsr = config->seed;
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
uint32_t bit = ((lfsr >> 31) ^ (lfsr >> 21) ^ (lfsr >> 1) ^ (lfsr >> 0)) & 1;
lfsr = (lfsr << 1) | bit;
float_word res;
res.word = lfsr;
uint32_t exponent = (lfsr >> 23) & 0xFF;
if (exponent & 0x80) {
exponent = 0x80 | (lfsr & 0x01);
}else {
exponent = 0x7C | (lfsr & 0x03);
}
res.word &= ~(0xFF << 23);
res.word |= (exponent << 23);
data_channel_write(data_channel_base, res.word);
}
return 0;
}

22
software/signal_processing/sine.c
View File

@ -1,10 +1,30 @@
#include "system/task_sine.h"
#include "system/hardware_task.h"
#include "system/sine_config.h"
#include "system/data_channel.h"
#include "system/float_word.h"
#include <math.h>
#include <stdio.h>
#include <limits.h>
#include <system.h>
int task_sine_run( void * data ) {
// TODO
sine_config * task = ( sine_config * ) data;
uint32_t data_channel_base = task-> base.sink;
data_channel_clear( data_channel_base );
for ( uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++ ) {
float_word res;
for(uint32_t y = 0; y < task->samples_per_periode; y++)
{
res.value = task->amplitude * sin(2*3.14/task->samples_per_periode*y + task->phase);
data_channel_write( data_channel_base, res.word );
}
}
return 0;
}

2
tests/hardware/task_fft/Makefile
View File

@ -11,8 +11,6 @@ verilog_srcs = \
vhdl_srcs = \
../../../hardware/system/reg32.vhd \
../../../hardware/system/avalon_slave.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../../hardware/test_data_channel.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/task.vhd \

4
tests/hardware/task_fft/test_task_fft.vhd
View File

@ -63,7 +63,7 @@ architecture test of test_task_fft is
variable writedata_float : float32;
variable writedata_real : real;
variable expected_real : real;
variable abs_err : real := 0.6;
variable abs_err : real := 0.5e-1;
variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
file data_file : text;
@ -110,13 +110,11 @@ architecture test of test_task_fft is
std.textio.write( data_file_fft, "]" & LF );
file_close( data_file_fft );
index := 0;
while index < STREAM_LEN loop
writedata_float := to_float( result( index ) );
writedata_real := to_real( writedata_float );
expected_real := work.fft_data.expected( index );
assert_near( writedata_real, expected_real, abs_err );
index := index + 1;
end loop;
file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );

1
tests/hardware/task_fft/vsim.wave
View File

@ -1,2 +1 @@
add wave -position end sim:/test_task_fft/dut/*
add wave -position end sim:/test_task_fft/dut/u_fft/*