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| Author | SHA1 | Date | |
|---|---|---|---|
|
22e222fab4 |
@ -30,8 +30,103 @@ architecture rtl of add is
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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type AddState is(
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ADD_IDLE,
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ADD_READ,
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ADD_CALC,
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ADD_STORERESULT
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);
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signal curAddState : ADDState;
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signal nextAddState : ADDState;
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signal a : std_logic_vector (31 downto 0);
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signal b : std_logic_vector (31 downto 0);
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signal startcore : std_logic;
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signal donecore : std_logic;
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signal sumcore : std_logic_vector (31 downto 0);
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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u_float_add : entity work.float_add
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port map(
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clk => clk,
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reset => reset,
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start => startcore,
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done => donecore,
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A => a,
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B => b,
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sum => sumcore
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);
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--Zuletzt haben wir den State transitions prozess angelegt. Ziegler nachfragen
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add_state_transitions : process (all) is
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begin
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--if(reset ='1' and rising_edge(clk)) then
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nextAddState <= curAddState;
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case curAddState is
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when ADD_IDLE =>
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if(current_task_state = work.task.TASK_RUNNING) then
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nextAddState <= ADD_CALC;
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end if;
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when ADD_READ =>
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nextAddState <= ADD_CALC;
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when ADD_CALC => Null;
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if(donecore = '1') then
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nextAddState <=ADD_STORERESULT;
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end if;
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when ADD_STORERESULT =>
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nextAddState <= ADD_READ;
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when others =>
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nextAddState <= curAddState;
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end case;
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end process add_state_transitions;
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add_process : process (clk,reset) is
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begin
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if(reset = '1') then
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curADDState <= ADD_CALC;
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index <= 0;
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signal_write <='0';
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signal_a_read <='0';
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signal_b_read <='0';
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startcore <= '0';
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signal_writedata <= (others => '0');
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b<= (others => '0');
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a<= (others => '0');
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elsif(rising_edge(clk)) then
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curAddState <= nextAddState;
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Case curAddState is
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when ADD_IDLE =>
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NULL;
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when ADD_READ =>
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signal_write <= '0';
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signal_a_read <= '1';
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signal_b_read <= '1';
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when ADD_CALC =>
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signal_a_read <= '0';
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signal_b_read <= '0';
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a <= signal_a_readdata;
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b <= signal_b_readdata;
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startcore <= '1';
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when ADD_STORERESULT =>
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startcore <= '0';
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signal_writedata <= sumcore;
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signal_write <= '1';
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index <= index+1;
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when others =>Null;
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end case;
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if(current_task_state=work.task.TASK_DONE)then
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index <= 0;
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signal_write <= '0';
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end if;
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end if;
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end process add_process;
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--
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task_state_transitions : process ( all ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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@ -40,7 +135,7 @@ begin
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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if ( index = work.task.STREAM_LEN ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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@ -54,21 +149,25 @@ begin
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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-- index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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NULL;
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-- index <= 0;
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-- signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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NULL;
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-- index <= index + 1;
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-- signal_write <= '1';
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-- signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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NULL;
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-- index <= 0;
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-- signal_write <= '0';
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end case;
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--test
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end if;
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end process sync;
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@ -1,76 +1,161 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity crc is
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port (
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clk : in std_logic;
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reset : in std_logic;
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entity crc is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity crc;
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity crc;
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architecture rtl of crc is
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architecture rtl of crc is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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-- function berechne_crc(crc_in : signed( 31 downto 0 ), data : signed( 31 downto 0 )) return signed;
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--Selbst angelegte Signale
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signal flag_index : bit := '0';
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signal crc_state : integer range 0 to 2;
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signal crcOut : std_logic_vector( 31 downto 0);
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signal crcIn : std_logic_vector( 31 downto 0) := x"FFFFFFFF";
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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--No Touchy
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end if;
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end process sync;
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end process task_state_transitions;
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task_state <= current_task_state;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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-- signal_write <= '0';
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when work.task.TASK_RUNNING =>
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if ( flag_index = '1' ) then
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index <= index + 1;
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end if;
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--signal_write <= '1';
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--signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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--signal_write <= '0';
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end case;
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end if;
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end process sync;
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end architecture rtl;
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crc_calc :process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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signal_read <= '0';
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signal_write <= '0';
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signal_writedata <= (others => '0');
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flag_index <= '0';
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elsif ( rising_edge( clk ) ) then
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case crc_state is --current oder next_calc_state
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when 0 =>
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signal_write <= '0';
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flag_index <= '0';
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if ( current_task_state = work.task.TASK_RUNNING ) then
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signal_read <= '1';
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crc_state <= 1;
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end if;
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when 1 =>
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signal_read <= '0';
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crcOut(0) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(16) xor crcIn(20) xor crcIn(22) xor crcIn(23) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(26);
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crcOut(1) <= crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(17) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(27);
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crcOut(2) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(18) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(28) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(28);
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crcOut(3) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(19) xor crcIn(23) xor crcIn(25) xor crcIn(26) xor crcIn(29) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(29);
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crcOut(4) <= crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(20) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(20) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(30);
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crcOut(5) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(21) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(21) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(31);
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crcOut(6) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(28) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(28) xor signal_readdata(29);
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crcOut(7) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(29) xor signal_readdata(30);
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crcOut(8) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
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crcOut(9) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(31);
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crcOut(10) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(13) xor crcIn(14) xor crcIn(18) xor crcIn(21) xor crcIn(22) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(26);
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crcOut(11) <= crcIn(1) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(10) xor crcIn(14) xor crcIn(15) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(27);
|
||||
crcOut(12) <= crcIn(2) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(11) xor crcIn(15) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28);
|
||||
crcOut(13) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(12) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29);
|
||||
crcOut(14) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(13) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(30);
|
||||
crcOut(15) <= crcIn(1) xor crcIn(2) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(14) xor crcIn(18) xor crcIn(19) xor crcIn(23) xor crcIn(26) xor crcIn(27) xor crcIn(31) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(31);
|
||||
crcOut(16) <= crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(15) xor crcIn(16) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28);
|
||||
crcOut(17) <= crcIn(2) xor crcIn(5) xor crcIn(8) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(8) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29);
|
||||
crcOut(18) <= crcIn(0) xor crcIn(3) xor crcIn(6) xor crcIn(9) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
|
||||
crcOut(19) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(18) xor crcIn(19) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
|
||||
crcOut(20) <= crcIn(0) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(17) xor crcIn(19) xor crcIn(22) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
|
||||
crcOut(21) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(12) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(12) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
|
||||
crcOut(22) <= crcIn(2) xor crcIn(7) xor crcIn(8) xor crcIn(13) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(13) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
|
||||
crcOut(23) <= crcIn(0) xor crcIn(3) xor crcIn(8) xor crcIn(9) xor crcIn(14) xor crcIn(19) xor crcIn(20) xor crcIn(21) xor crcIn(23) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(14) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
|
||||
crcOut(24) <= crcIn(2) xor crcIn(3) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(15) xor crcIn(16) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
|
||||
crcOut(25) <= crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
|
||||
crcOut(26) <= crcIn(2) xor crcIn(3) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
|
||||
crcOut(27) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(16) xor crcIn(19) xor crcIn(20) xor crcIn(23) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
|
||||
crcOut(28) <= crcIn(0) xor crcIn(4) xor crcIn(6) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
|
||||
crcOut(29) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(7) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
|
||||
crcOut(30) <= crcIn(3) xor crcIn(4) xor crcIn(7) xor crcIn(14) xor crcIn(15) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
|
||||
crcOut(31) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(15) xor crcIn(19) xor crcIn(21) xor crcIn(22) xor crcIn(25) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(31);
|
||||
|
||||
crc_state <= 2; --Calc Zustand aendern
|
||||
when 2 =>
|
||||
if ( current_task_state = work.task.TASK_DONE ) then
|
||||
signal_writedata <= not crcOut; --Ergebnis invertieren
|
||||
signal_write <= '1';
|
||||
end if;
|
||||
|
||||
flag_index <= '1'; --flag_index sagt nur, dass der index hochgezaehlt werden soll
|
||||
crc_state <= 0; --Calc Zustand aendern
|
||||
-- assign new crc value
|
||||
crcIn <= crcOut;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process crc_calc;
|
||||
|
||||
|
||||
task_state <= current_task_state;
|
||||
|
||||
end architecture rtl;
|
||||
|
||||
|
||||
@ -1,26 +1,13 @@
|
||||
------------------------------------------------------------------------
|
||||
-- fft
|
||||
--
|
||||
-- calculation of FFT magnitudes
|
||||
-- calculation of FFT magnitude
|
||||
--
|
||||
-- Inputs:
|
||||
-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
|
||||
--
|
||||
-- Outputs
|
||||
-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
|
||||
--
|
||||
--
|
||||
-- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor
|
||||
-- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist)
|
||||
-- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln
|
||||
-- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0)
|
||||
-- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich)
|
||||
-- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float)
|
||||
-- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32).
|
||||
-- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist)
|
||||
-- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html)
|
||||
-- (z.B: ein Array verwenden, um die Werte zu sortieren)
|
||||
-- Dann das Ergebnis in den Ausgangsfifo speichern
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
library ieee;
|
||||
@ -35,10 +22,10 @@ library work;
|
||||
entity fft is
|
||||
generic (
|
||||
|
||||
-- input data width of real/img part
|
||||
-- input data width of real/img part
|
||||
input_data_width : integer := 32;
|
||||
|
||||
-- output data width of real/img part
|
||||
-- output data width of real/img part
|
||||
output_data_width : integer := 32
|
||||
|
||||
);
|
||||
@ -48,10 +35,10 @@ entity fft is
|
||||
|
||||
task_start : in std_logic;
|
||||
task_state : out work.task.State;
|
||||
|
||||
|
||||
signal_read : out std_logic;
|
||||
signal_readdata : in std_logic_vector( 31 downto 0 );
|
||||
|
||||
|
||||
signal_write : out std_logic;
|
||||
signal_writedata : out std_logic_vector( 31 downto 0 )
|
||||
);
|
||||
@ -59,103 +46,12 @@ end entity fft;
|
||||
|
||||
architecture rtl of fft is
|
||||
|
||||
|
||||
-- Signale für Task State Machine
|
||||
signal current_task_state : work.task.State;
|
||||
signal next_task_state : work.task.State;
|
||||
signal index : integer range 0 to work.task.STREAM_LEN;
|
||||
--signal index : integer range 0 to 2000;
|
||||
|
||||
-- component des Verilog IP-Cores fuer die FFT
|
||||
component fftmain is
|
||||
port(
|
||||
clock: in std_logic; -- Master Clock
|
||||
reset: in std_logic; -- Active High Asynchronous Reset
|
||||
di_en: in std_logic; -- Input Data Enable
|
||||
di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
|
||||
di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
|
||||
do_en: out std_logic; -- Output Data Enable
|
||||
do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
|
||||
do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
|
||||
);
|
||||
end component;
|
||||
|
||||
-- Signale Input skaliert
|
||||
signal fft_float_input : signed( 31 downto 0 );
|
||||
signal fft_float_scaled_input : signed( 31 downto 0 );
|
||||
|
||||
-- Signale fuer FFT-IP Core
|
||||
-- fft data input signal
|
||||
signal fft_input_data_enable: std_logic;
|
||||
signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
|
||||
signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
|
||||
-- fft output data
|
||||
signal fft_output_valid : std_logic;
|
||||
signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
|
||||
signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
|
||||
|
||||
-- Signale fuer Magnitude IP-Core
|
||||
signal fft_mag_calc_valid : std_logic;
|
||||
signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
|
||||
|
||||
-- Signale fuer Ergebnis skaliert
|
||||
signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);
|
||||
signal fft_float_scaled : signed( 31 downto 0 );
|
||||
|
||||
-- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
|
||||
|
||||
signal data_memory : work.reg32.RegArray( 0 to 1023 );
|
||||
signal index_reversed : std_logic_vector(9 downto 0);
|
||||
signal index_output_sv : std_logic_vector(9 downto 0);
|
||||
signal index_output : integer range 0 to 1023;
|
||||
|
||||
-- Signal um in den Write FIFO zu schreiben
|
||||
signal wr_fifo : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Hier muss der Verilog FFT IP-Core instanziert werden
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
--u_fft : fftmain
|
||||
-- port map (
|
||||
-- clock => , -- system clock
|
||||
-- reset => , -- Active High Asynchronous Reset
|
||||
-- di_en => , -- Input Data Enable
|
||||
-- di_re => , -- Input Data (Real)
|
||||
-- di_im => , -- Input Data (Imag)
|
||||
-- do_en => , -- Output Data Enable
|
||||
-- do_re => , -- Output Data (Real)
|
||||
-- do_im => -- Output Data (Imag)
|
||||
-- );
|
||||
|
||||
fft_output_valid <= '0';
|
||||
data_out_re <= (others => '0');
|
||||
data_out_im <= (others => '0');
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Hier muss der VHDL Magnitue IP-COre instanziert werden
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
-- u_fft_mag_calc : entity work.fft_magnitude_calc
|
||||
-- port map (
|
||||
-- clk => , -- system clock
|
||||
-- reset => , -- Active High Asynchronous Reset
|
||||
-- input_valid => , -- Input Data Valid
|
||||
-- input_re => , -- Input Realteil in Fixpoint format
|
||||
-- input_im => , -- Input Imaginaerteil in Fixpoint format
|
||||
-- output_valid => , -- Output Data Valid
|
||||
-- output_magnitude => -- Magnitude Output in Fixpoint format
|
||||
-- );
|
||||
|
||||
fft_mag_calc_valid <= '1' when index = 0 else '0';
|
||||
fft_mag_calc_result <= (others => '0');
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
|
||||
-----------------------------------------------------------------------------------------------
|
||||
task_state_transitions : process (all) is
|
||||
task_state_transitions : process ( current_task_state, task_start, index ) is
|
||||
begin
|
||||
next_task_state <= current_task_state;
|
||||
case current_task_state is
|
||||
@ -164,7 +60,7 @@ begin
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
when work.task.TASK_RUNNING =>
|
||||
if ( index = 2 ) then
|
||||
if ( index = work.task.STREAM_LEN - 1 ) then
|
||||
next_task_state <= work.task.TASK_DONE;
|
||||
end if;
|
||||
when work.task.TASK_DONE =>
|
||||
@ -174,157 +70,28 @@ begin
|
||||
end case;
|
||||
end process task_state_transitions;
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
-- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
|
||||
-----------------------------------------------------------------------------------------------
|
||||
sync : process ( clk, reset ) is
|
||||
sync : process ( clk, reset ) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
current_task_state <= work.task.TASK_IDLE;
|
||||
index <= 0;
|
||||
wr_fifo <= '0';
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
current_task_state <= next_task_state;
|
||||
wr_fifo <= '0';
|
||||
case next_task_state is
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
when work.task.TASK_RUNNING =>
|
||||
-- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
|
||||
-- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
|
||||
if ( index_output = work.task.STREAM_LEN - 1 ) then
|
||||
index <= index + 1;
|
||||
end if;
|
||||
if index = 1 then
|
||||
wr_fifo <= '1';
|
||||
end if;
|
||||
when work.task.TASK_DONE => null;
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
when work.task.TASK_RUNNING =>
|
||||
index <= index + 1;
|
||||
signal_write <= '1';
|
||||
signal_writedata <= ( others => '0' );
|
||||
when work.task.TASK_DONE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
end case;
|
||||
end if;
|
||||
end process sync;
|
||||
|
||||
end process sync;
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
|
||||
-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
|
||||
-- und im naechsten Takt schon weiter verarbeitet werden können
|
||||
--
|
||||
-- Erforderliches Scaling:
|
||||
--
|
||||
-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
|
||||
-- multiplication is a simple addition of the exponents.
|
||||
-- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
|
||||
-- This means an divsion through 16 -> exponent needs an addition of - 4
|
||||
--
|
||||
-- fft_float_input = gelesener Wert vom FIFO (floating point)
|
||||
-- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
|
||||
-- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
fft_float_input <= signed(signal_readdata);
|
||||
|
||||
fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
|
||||
-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
|
||||
-- und im naechsten Takt schon weiter verarbeitet werden können
|
||||
--
|
||||
-- Erforderliches Scaling:
|
||||
--
|
||||
-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
|
||||
-- multiplication is a simple addition of the exponents.
|
||||
-- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16
|
||||
-- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
|
||||
-- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
|
||||
-- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
|
||||
--
|
||||
-- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
|
||||
-- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
|
||||
|
||||
fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
|
||||
-- Umordnung der Ausgangswerte erfolgen
|
||||
--
|
||||
-- index_output_sv = std_logic_vector des Integer Ausgangsindex
|
||||
-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
|
||||
--
|
||||
c_index_output_sv:
|
||||
index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
|
||||
c_reversed_index:
|
||||
index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Prozess steuert das hochzaehlen des Ausgang Index
|
||||
-----------------------------------------------------------------------------------------------
|
||||
p_number_output_sample: process ( clk, reset ) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
index_output <= 0;
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
-- Ruecksetz Bedingung für index_output
|
||||
if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
|
||||
index_output <= 0;
|
||||
-- index_output hochzaehlen um in natural order im array zu speichern
|
||||
elsif fft_mag_calc_valid = '1' then
|
||||
index_output <= index_output + 1;
|
||||
-- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
|
||||
elsif wr_fifo = '1' then
|
||||
index_output <= index_output + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_number_output_sample;
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Prozess speichert das skalierte Endergbenis iun der natural order
|
||||
-----------------------------------------------------------------------------------------------
|
||||
p_output2float_memory: process ( clk, reset) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
null;
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
if fft_mag_calc_valid = '1' then
|
||||
data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
|
||||
end if;
|
||||
end if;
|
||||
end process p_output2float_memory;
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Schreiben der berechneten Werte in den FIFO
|
||||
-----------------------------------------------------------------------------------------------
|
||||
p_output_fifo: process ( clk, reset ) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
signal_writedata <= (others => '0');
|
||||
signal_write <= '0';
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
signal_write <= '0';
|
||||
if wr_fifo = '1' then
|
||||
signal_writedata <= data_memory(index_output);
|
||||
signal_write <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process p_output_fifo;
|
||||
|
||||
|
||||
-- Hier sollen die sonstigen benoetigten Anweisungen stehen
|
||||
task_state <= current_task_state;
|
||||
task_state <= current_task_state;
|
||||
|
||||
end architecture rtl;
|
||||
|
||||
@ -1,77 +1,164 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.reg32.all;
|
||||
use work.float.all;
|
||||
use work.task.all;
|
||||
library work;
|
||||
use work.reg32.all;
|
||||
use work.float.all;
|
||||
use work.task.all;
|
||||
|
||||
entity sine is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
entity sine is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
task_start : in std_logic;
|
||||
task_state : out work.task.State;
|
||||
task_start : in std_logic;
|
||||
task_state : out work.task.State;
|
||||
|
||||
step_size : in work.reg32.word;
|
||||
phase : in work.reg32.word;
|
||||
amplitude : in work.reg32.word;
|
||||
step_size : in work.reg32.word;
|
||||
phase : in work.reg32.word;
|
||||
amplitude : in work.reg32.word;
|
||||
|
||||
signal_write : out std_logic;
|
||||
signal_writedata : out std_logic_vector( 31 downto 0 )
|
||||
);
|
||||
end entity sine;
|
||||
signal_write : out std_logic;
|
||||
signal_writedata : out std_logic_vector( 31 downto 0 )
|
||||
);
|
||||
end entity sine;
|
||||
|
||||
architecture rtl of sine is
|
||||
architecture rtl of sine is
|
||||
|
||||
signal current_task_state : work.task.State;
|
||||
signal next_task_state : work.task.State;
|
||||
signal index : integer range 0 to work.task.STREAM_LEN;
|
||||
signal current_task_state : work.task.State; --multiple sources
|
||||
signal next_task_state : work.task.State;
|
||||
signal index : integer range 0 to work.task.STREAM_LEN; --multiple sources
|
||||
|
||||
--Selbst angelegte Signal:
|
||||
signal data_valid_flag : std_logic;
|
||||
signal busy_flag : std_logic;
|
||||
signal result_valid_flag : std_logic;
|
||||
signal angle_sig : signed( 31 downto 0);
|
||||
signal ergebnis : signed( 31 downto 0 );
|
||||
signal ampl_sig : signed( 31 downto 0 );
|
||||
|
||||
--Zustände für die Zustandsmaschine für die Berechnung
|
||||
type CalcState is (
|
||||
CALC_IDLE,
|
||||
CALC_START,
|
||||
CALC_SINE,
|
||||
CALC_STORE_RESULT
|
||||
);
|
||||
--Signale für die Zustandsmaschine für die Berechnung
|
||||
signal current_calc_state : CalcState;
|
||||
signal next_calc_state : CalcState;
|
||||
|
||||
begin
|
||||
task_state_transitions : process ( current_task_state, task_start, index ) is
|
||||
begin
|
||||
next_task_state <= current_task_state;
|
||||
case current_task_state is
|
||||
when work.task.TASK_IDLE =>
|
||||
if ( task_start = '1' ) then
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
when work.task.TASK_RUNNING =>
|
||||
if ( index = work.task.STREAM_LEN - 1 ) then
|
||||
next_task_state <= work.task.TASK_DONE;
|
||||
end if;
|
||||
when work.task.TASK_DONE =>
|
||||
if ( task_start = '1' ) then
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
end case;
|
||||
end process task_state_transitions;
|
||||
u_float_sine : entity work.float_sine -- Das hier ist der Core!
|
||||
generic map (
|
||||
ITERATIONS => 8
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
data_valid => data_valid_flag, --# load new input data
|
||||
busy => busy_flag, --# generating new result
|
||||
result_valid => result_valid_flag, --# flag when result is valid
|
||||
angle => angle_sig, -- angle in brads (2**size brads = 2*pi radians)
|
||||
sine => ergebnis --Hierzu nachfragen
|
||||
);
|
||||
|
||||
sync : process ( clk, reset ) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
current_task_state <= work.task.TASK_IDLE;
|
||||
index <= 0;
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
current_task_state <= next_task_state;
|
||||
case next_task_state is
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
when work.task.TASK_RUNNING =>
|
||||
index <= index + 1;
|
||||
signal_write <= '1';
|
||||
signal_writedata <= ( others => '0' );
|
||||
when work.task.TASK_DONE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
--Bei diesem task nichts ändern!
|
||||
task_state_transitions : process ( all ) is
|
||||
begin
|
||||
next_task_state <= current_task_state;
|
||||
case current_task_state is
|
||||
when work.task.TASK_IDLE =>
|
||||
if ( task_start = '1' ) then
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
when work.task.TASK_RUNNING =>
|
||||
if ( index = work.task.STREAM_LEN - 1 ) then
|
||||
next_task_state <= work.task.TASK_DONE;
|
||||
end if;
|
||||
when work.task.TASK_DONE =>
|
||||
if ( task_start = '1' ) then
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process sync;
|
||||
end process task_state_transitions;
|
||||
|
||||
task_state <= current_task_state;
|
||||
|
||||
end architecture rtl;
|
||||
--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Fertig
|
||||
calc_state_transitions: process (all) is
|
||||
begin
|
||||
next_calc_state <= current_calc_state;
|
||||
case current_calc_state is
|
||||
when CALC_IDLE=>
|
||||
if (current_task_state= work.task.TASK_RUNNING) then
|
||||
next_calc_state <= CALC_START;
|
||||
end if;
|
||||
when CALC_START=>
|
||||
next_calc_state <= CALC_SINE;
|
||||
when CALC_SINE =>
|
||||
if (result_valid_flag = '1' and busy_flag = '0') then --or falling_edge( busy) ?
|
||||
next_calc_state <= CALC_STORE_RESULT;
|
||||
end if;
|
||||
when CALC_STORE_RESULT =>
|
||||
if ( index = work.task.STREAM_LEN ) then
|
||||
next_calc_state <= CALC_IDLE;
|
||||
else
|
||||
next_calc_state <= CALC_START;
|
||||
end if;
|
||||
end case;
|
||||
end process calc_state_transitions;
|
||||
|
||||
|
||||
--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks
|
||||
task_sync : process (clk, reset) is
|
||||
begin
|
||||
if (reset = '1') then
|
||||
current_task_state <= work.task.TASK_IDLE;
|
||||
|
||||
elsif (rising_edge( clk)) then
|
||||
current_task_state <= next_task_state;
|
||||
case next_task_state is
|
||||
when work.task. TASK_IDLE => null;
|
||||
when work.task. TASK_RUNNING => null;
|
||||
when work.task. TASK_DONE => null;
|
||||
end case;
|
||||
end if;
|
||||
end process task_sync;
|
||||
|
||||
--Zustandsspeicher und Ausgangsschaltnetz zu Berechnung
|
||||
sync : process (clk, reset) is
|
||||
begin
|
||||
if (reset = '1') then
|
||||
index <= 0;
|
||||
data_valid_flag <= '0';
|
||||
current_calc_state <= CALC_IDLE;
|
||||
--ergebnis <= (others => '0'); --Wird von IP Core gesteuert und darf deshalb hier nicht getrieben werden
|
||||
signal_writedata <= (others => '0');
|
||||
signal_write <= '0';
|
||||
angle_sig <= (others => '0');
|
||||
elsif (rising_edge( clk)) then
|
||||
current_calc_state <= next_calc_state;
|
||||
case next_calc_state is
|
||||
when CALC_IDLE =>
|
||||
data_valid_flag <= '0';
|
||||
signal_write <= '0';
|
||||
angle_sig <= signed (phase);
|
||||
ampl_sig <= signed (amplitude);
|
||||
when CALC_START =>
|
||||
data_valid_flag <= '1';
|
||||
signal_write <= '0';
|
||||
angle_sig <= angle_sig + signed(step_size); --step_size = 2 * PI / 32
|
||||
when CALC_SINE => --hier Berechnung mit IP Core?
|
||||
data_valid_flag <= '0';
|
||||
when CALC_STORE_RESULT =>
|
||||
index <= index + 1;
|
||||
signal_write <= '1';
|
||||
--Berechne float multiplikation zu Fuss. Exponent + Exponent usw.
|
||||
signal_writedata <= std_logic_vector( ergebnis(31 downto 31) & (ergebnis(30 downto 23) + (signed(ampl_sig(30 downto 23)) - 127)) & ergebnis(22 downto 0));
|
||||
end case;
|
||||
end if;
|
||||
end process sync;
|
||||
task_state <= current_task_state;
|
||||
|
||||
end architecture rtl;
|
||||
|
||||
@ -5,7 +5,16 @@
|
||||
int task_add_run( void * task ) {
|
||||
|
||||
// TODO
|
||||
|
||||
add_config * config = (add_config *) task;
|
||||
for( uint32_t i=0; i< DATA_CHANNEL_DEPTH; ++i)
|
||||
{
|
||||
float a,b;
|
||||
float_word c;
|
||||
data_channel_read(config->sources [0],(uint32_t * ) & a);
|
||||
data_channel_read(config->sources [1],(uint32_t * ) & b);
|
||||
c.value = a+b;
|
||||
data_channel_write( config->sink, c.word);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1,11 +1,57 @@
|
||||
#include "system/task_crc.h"
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
#include <stdio.h>
|
||||
|
||||
|
||||
// Funktion zur Berechnung des CRC32
|
||||
void berechne_crc32(uint32_t data, uint32_t * crc);
|
||||
void crc32( uint32_t data, uint32_t* crc );
|
||||
|
||||
int task_crc_run( void * task ) {
|
||||
crc_config * config = (crc_config*) task;
|
||||
uint32_t value = config->start;
|
||||
// Nachfolgende Antworten Lesen den FIFO der ersten Datenquelle aus und multiplizieren
|
||||
// den jeweils gelesenen Wert mit 4 und speichern das Ergebnis in der Datensenke
|
||||
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
|
||||
float_word a;
|
||||
data_channel_read(config->base.sources[0], (uint32_t * ) & a.value );
|
||||
if (i<10) {printf("\n Input %i DATA; %x\ CRC: %x\n", i, a.word, value);}
|
||||
berechne_crc32(a.word, &value); //Startwert jedes Mal, oder mit vorheriger crc starten?
|
||||
if (i<10) {printf("\n CRC Zwischenwert Output(%i): %x\n", i, value);}
|
||||
}
|
||||
printf("CRC Wert: %x\n", value);
|
||||
data_channel_write( config->base.sink, value);
|
||||
|
||||
// TODO
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void berechne_crc32(uint32_t data, uint32_t * crc) {
|
||||
uint32_t bytes[4]; //Reihenfolge richtig?
|
||||
uint32_t reg32 = ~*crc;
|
||||
|
||||
bytes[0] = (uint32_t) (data) & 0x000000FF;
|
||||
bytes[1] = (uint32_t) (data >>8) & 0x000000FF;
|
||||
bytes[2] = (uint32_t) (data >>16) & 0x000000FF;
|
||||
bytes[3] = (uint32_t) (data >>24) & 0x000000FF; //aufffüllen
|
||||
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
//von rechts nch links
|
||||
for (uint8_t j = 0; j <8; j++) {
|
||||
|
||||
// Prüfen, ob das am weitesten rechts stehende Bit von crc 1 ist
|
||||
if ((reg32 & 1) != (bytes[i] & 1)) { //Wieso crc & 1?
|
||||
reg32 = (reg32 >> 1)^CRC32POLY; // XOR mit dem Polynom
|
||||
} else {
|
||||
reg32 >>= 1;
|
||||
}
|
||||
bytes[i]>>=1;
|
||||
}
|
||||
*crc = reg32 ^0xFFFFFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,10 +1,29 @@
|
||||
#include "system/task_sine.h"
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
//Aus dem Skript kopiert:
|
||||
#include "system/task_sine.h"
|
||||
#include "system/hardware_task.h"
|
||||
#include "system/sine_config.h"
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
#include <math.h>
|
||||
#include <stdio.h>
|
||||
#include <limits.h>
|
||||
#include <system.h>
|
||||
|
||||
int task_sine_run( void * data ) {
|
||||
int task_sine_run( void * data) {
|
||||
|
||||
// TODO
|
||||
// Nachfolgende Anweisungen Schreiben 1024 Mal den Wert 4 in den FIFO für Sinus
|
||||
sine_config * task = (sine_config * ) data;
|
||||
uint32_t data_channel_base = task->base.sink;
|
||||
data_channel_clear( data_channel_base );
|
||||
|
||||
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
|
||||
|
||||
float_word res;
|
||||
res.value = task->amplitude * sin(task->phase + i *2 * M_PI / task->samples_per_periode);
|
||||
|
||||
data_channel_write( data_channel_base, res.word );
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -11,8 +11,6 @@ verilog_srcs = \
|
||||
vhdl_srcs = \
|
||||
../../../hardware/system/reg32.vhd \
|
||||
../../../hardware/system/avalon_slave.vhd \
|
||||
../test_utility.vhd \
|
||||
../test_avalon_slave.vhd \
|
||||
../../hardware/test_data_channel.vhd \
|
||||
../../../hardware/system/avalon_slave_transitions.vhd \
|
||||
../../../hardware/system/task.vhd \
|
||||
|
||||
@ -63,7 +63,7 @@ architecture test of test_task_fft is
|
||||
variable writedata_float : float32;
|
||||
variable writedata_real : real;
|
||||
variable expected_real : real;
|
||||
variable abs_err : real := 0.6;
|
||||
variable abs_err : real := 0.5e-1;
|
||||
variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
|
||||
variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
|
||||
file data_file : text;
|
||||
@ -110,13 +110,11 @@ architecture test of test_task_fft is
|
||||
std.textio.write( data_file_fft, "]" & LF );
|
||||
file_close( data_file_fft );
|
||||
|
||||
index := 0;
|
||||
while index < STREAM_LEN loop
|
||||
writedata_float := to_float( result( index ) );
|
||||
writedata_real := to_real( writedata_float );
|
||||
expected_real := work.fft_data.expected( index );
|
||||
assert_near( writedata_real, expected_real, abs_err );
|
||||
index := index + 1;
|
||||
end loop;
|
||||
|
||||
file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );
|
||||
|
||||
@ -1,2 +1 @@
|
||||
add wave -position end sim:/test_task_fft/dut/*
|
||||
add wave -position end sim:/test_task_fft/dut/u_fft/*
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user