library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity rand is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;
        seed : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity rand;

architecture rtl of rand is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

    -- Register für den LFSR Zustand
    signal lfsr_reg : std_logic_vector(31 downto 0);

begin
    
    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
        variable v_feedback : std_logic;
        variable v_lfsr_next : std_logic_vector(31 downto 0);

		variable v_send_cycle : boolean := true;	-- toggle um signal_write nur einen Takt auszugeben
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
            lfsr_reg <= (others => '0');
            signal_write <= '0';
            signal_writedata <= (others => '0');
			v_send_cycle := true;

        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;

            case next_task_state is
           		when work.task.TASK_IDLE =>
                	index <= 0;
                	signal_write <= '0';
                	lfsr_reg <= seed;
					v_send_cycle := true; -- Reset toggle für nächsten Start
            	when work.task.TASK_RUNNING =>
					if v_send_cycle = true then
		            	index <= index + 1;
		            	-- 1. LFSR Feedback berechnen (Polynom x^31 + x^21 + x^1 + 1)
		            	v_feedback := lfsr_reg(31) xor lfsr_reg(21) xor lfsr_reg(1) xor lfsr_reg(0);  
		            	-- 2. Schieben und neues Bit einfügen
		            	v_lfsr_next := lfsr_reg(30 downto 0) & v_feedback;               
		            	-- Register aktualisieren für den nächsten Takt
		            	lfsr_reg <= v_lfsr_next;
		            	-- 3. Daten schreiben und Bit-Manipulation 
		            	signal_write <= '1';               
		            	-- Wir nutzen hier v_lfsr_next, damit der geschriebene Wert 
		            	-- dem aktuellen Berechnungsschritt entspricht.
		            	if v_lfsr_next(30) = '1' then
		                	-- Fall A: Bit 30 ist 1. Bits 29-24 löschen 
		                	-- Maske: AND mit 1100 0000 ... (0xC0...)
		                	signal_writedata <= v_lfsr_next and x"C0FFFFFF";
		            	else
		                	-- Fall B: Bit 30 ist 0. Bits 29-25 setzen 
		                	-- Maske: OR mit 0011 1110 ... (0x3E...)
		                	signal_writedata <= v_lfsr_next or x"3E000000";
		            	end if;
					
						v_send_cycle := false;
					else
						signal_write <= '0';
						v_send_cycle := true;
					end if;

            	when work.task.TASK_DONE =>
                	index <= 0;
                	signal_write <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;