# TCL File Generated by Component Editor 21.1 # Fri Sep 09 13:42:23 CEST 2022 # DO NOT MODIFY # # data_channel "data_channel" v1.0 # Johannes Kutning 2022.09.09.13:42:23 # A data channel for signal data transport # # # request TCL package from ACDS 16.1 # package require -exact qsys 16.1 # # module data_channel # set_module_property DESCRIPTION "A data channel for signal data transport" set_module_property NAME data_channel set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP signal_processing set_module_property AUTHOR "Johannes Kutning" set_module_property DISPLAY_NAME data_channel set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL data_channel set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file data_channel.vhd VHDL PATH hardware/system/data_channel.vhd TOP_LEVEL_FILE # # parameters # add_parameter DEPTH POSITIVE 1024 set_parameter_property DEPTH DEFAULT_VALUE 1024 set_parameter_property DEPTH DISPLAY_NAME DEPTH set_parameter_property DEPTH TYPE POSITIVE set_parameter_property DEPTH UNITS None set_parameter_property DEPTH ALLOWED_RANGES 1:2147483647 set_parameter_property DEPTH HDL_PARAMETER true # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset # add_interface reset reset end set_interface_property reset associatedClock clock set_interface_property reset synchronousEdges DEASSERT set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset CMSIS_SVD_VARIABLES "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset reset reset Input 1 # # connection point ctrl # add_interface ctrl avalon end set_interface_property ctrl addressUnits WORDS set_interface_property ctrl associatedClock clock set_interface_property ctrl associatedReset reset set_interface_property ctrl bitsPerSymbol 8 set_interface_property ctrl burstOnBurstBoundariesOnly false set_interface_property ctrl burstcountUnits WORDS set_interface_property ctrl explicitAddressSpan 0 set_interface_property ctrl holdTime 0 set_interface_property ctrl linewrapBursts false set_interface_property ctrl maximumPendingReadTransactions 0 set_interface_property ctrl maximumPendingWriteTransactions 0 set_interface_property ctrl readLatency 0 set_interface_property ctrl readWaitTime 1 set_interface_property ctrl setupTime 0 set_interface_property ctrl timingUnits Cycles set_interface_property ctrl writeWaitTime 0 set_interface_property ctrl ENABLED true set_interface_property ctrl EXPORT_OF "" set_interface_property ctrl PORT_NAME_MAP "" set_interface_property ctrl CMSIS_SVD_VARIABLES "" set_interface_property ctrl SVD_ADDRESS_GROUP "" add_interface_port ctrl ctrl_address address Input 4 add_interface_port ctrl ctrl_read read Input 1 add_interface_port ctrl ctrl_readdata readdata Output 32 add_interface_port ctrl ctrl_write write Input 1 add_interface_port ctrl ctrl_writedata writedata Input 32 set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 # # connection point hw_sink # add_interface hw_sink avalon end set_interface_property hw_sink addressUnits WORDS set_interface_property hw_sink associatedClock clock set_interface_property hw_sink associatedReset reset set_interface_property hw_sink bitsPerSymbol 8 set_interface_property hw_sink burstOnBurstBoundariesOnly false set_interface_property hw_sink burstcountUnits WORDS set_interface_property hw_sink explicitAddressSpan 0 set_interface_property hw_sink holdTime 0 set_interface_property hw_sink linewrapBursts false set_interface_property hw_sink maximumPendingReadTransactions 0 set_interface_property hw_sink maximumPendingWriteTransactions 0 set_interface_property hw_sink readLatency 0 set_interface_property hw_sink readWaitTime 1 set_interface_property hw_sink setupTime 0 set_interface_property hw_sink timingUnits Cycles set_interface_property hw_sink writeWaitTime 0 set_interface_property hw_sink ENABLED true set_interface_property hw_sink EXPORT_OF "" set_interface_property hw_sink PORT_NAME_MAP "" set_interface_property hw_sink CMSIS_SVD_VARIABLES "" set_interface_property hw_sink SVD_ADDRESS_GROUP "" add_interface_port hw_sink hw_sink_write write Input 1 add_interface_port hw_sink hw_sink_writedata writedata Input 32 set_interface_assignment hw_sink embeddedsw.configuration.isFlash 0 set_interface_assignment hw_sink embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment hw_sink embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment hw_sink embeddedsw.configuration.isPrintableDevice 0 # # connection point hw_source # add_interface hw_source avalon end set_interface_property hw_source addressUnits WORDS set_interface_property hw_source associatedClock clock set_interface_property hw_source associatedReset reset set_interface_property hw_source bitsPerSymbol 8 set_interface_property hw_source burstOnBurstBoundariesOnly false set_interface_property hw_source burstcountUnits WORDS set_interface_property hw_source explicitAddressSpan 0 set_interface_property hw_source holdTime 0 set_interface_property hw_source linewrapBursts false set_interface_property hw_source maximumPendingReadTransactions 0 set_interface_property hw_source maximumPendingWriteTransactions 0 set_interface_property hw_source readLatency 0 set_interface_property hw_source readWaitTime 1 set_interface_property hw_source setupTime 0 set_interface_property hw_source timingUnits Cycles set_interface_property hw_source writeWaitTime 0 set_interface_property hw_source ENABLED true set_interface_property hw_source EXPORT_OF "" set_interface_property hw_source PORT_NAME_MAP "" set_interface_property hw_source CMSIS_SVD_VARIABLES "" set_interface_property hw_source SVD_ADDRESS_GROUP "" add_interface_port hw_source hw_source_read read Input 1 add_interface_port hw_source hw_source_readdata readdata Output 32 set_interface_assignment hw_source embeddedsw.configuration.isFlash 0 set_interface_assignment hw_source embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment hw_source embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment hw_source embeddedsw.configuration.isPrintableDevice 0