library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity rand is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;
        seed : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity rand;

architecture rtl of rand is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
    
    signal f_start : std_logic := '0';
	signal f_done : std_logic := '0';
	signal f_A : std_logic_vector(31 downto 0) := (others => '0');
	signal f_B : std_logic_vector(31 downto 0) := (others => '0');
	signal f_sum : std_logic_vector(31 downto 0) := (others => '0');

begin
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u_float_rand : entity work.float_rand --Zugriff auf die Float_ datei 
	port map (
		clk => clk,
		reset => reset,
		start => f_start,
		done => f_done, 
		A => f_A,
		B => f_B,
		sum => f_sum
	);
	
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    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;
    
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    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
            f_start <= '0';
            signal_a_read <= '0';
            signal_b_read <= '0';
            signal_write <= '0';
            f_A <= (others => '0');
            f_B <= (others => '0');
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
                signal_a_read <= '0';
                signal_b_read <= '0';
                f_start <= '0';
                signal_write <= '0';
                signal_writedata <= (others => '0');
            when work.task.TASK_RUNNING =>
                if f_start = '0' and f_done = '0' then 
                	--FIFO lesen
                	signal_a_read <= '1';
                	signal_b_read <= '1'; 
                	f_A <= signal_a_readdata;
 					f_B <= signal_b_readdata;
 					f_start <= '1';
                	signal_write <= '0';
                elsif f_start = '1' and f_done = '0' then 
                	--Startet nur einen tAKT
                	signal_a_read <= '0';
                	signal_b_read <= '0';
                elsif f_start ='1' and f_done = '1' then 
                	--Ergebnisse speiecern
                	f_start <= '0';
                	signal_write <= '1';
                	signal_writedata <= f_sum;
                	--signal_write <= '0';
                	--signal_writedata <= ( others => '0' );
            		--Index erhöhen
            		--if index < work.task.STREAM_LEN -1 then 
            		index <= index + 1;
            			--end if;
            		else signal_write <= '0';
   					end if;         			
                --index <= index + 1;
               -- signal_write <= '1';
               -- signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                index <= 0;
                signal_write <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;