library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )


    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
    SIGNAL float_sum : STD_LOGIC_VECTOR(31 downto 0);
    SIGNAL fa_start: std_logic;
    SIGNAl fa_done: std_logic;

begin

    u_float_add : entity work.float_add
	port map(
		clk => clk,
		reset => reset,
		start => fa_start,
		done => fa_done,
		A => signal_a_readdata,
		B => signal_b_readdata,
		sum => float_sum
		);		


    -- Zustandsübergangslogik:
    -- in TASK_RUNNING erst dann nach TASK_DONE, wenn die letzte Addition fertig ist
    task_state_transitions : process ( current_task_state, task_start, index, fa_done ) is
    begin
        next_task_state <= current_task_state;

        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;

            when work.task.TASK_RUNNING =>
                if ( fa_done = '1' and index = work.task.STREAM_LEN -1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;

            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index              <= 0;

            signal_write       <= '0';
            signal_a_read      <= '0';
            signal_b_read      <= '0';
           -- signal_writedata   <= (others => '0');
            fa_start           <= '0';

        elsif ( rising_edge( clk ) ) then
            -- Zustand updaten
            current_task_state <= next_task_state;

            case current_task_state is
                when work.task.TASK_IDLE =>
                    index            <= 0;
                    signal_write     <= '0';
                    signal_a_read    <= '0';
                    signal_b_read    <= '0';
                  --  signal_writedata <= (others => '0');
                    fa_start         <= '0';

                when work.task.TASK_RUNNING =>
                    -- Standardwerte im RUNNING-Zustand
                    signal_write  <= '0';   -- nur bei fertig berechneter Summe auf '1'
                    signal_a_read <= '0';
                    signal_b_read <= '0';

                   
                    if (fa_start = '0' and fa_done = '0') then
                        -- neue Addition starten: Daten anfordern und start setzen
                        signal_a_read <= '1';
                        signal_b_read <= '1';
                        fa_start      <= '1';

                    elsif (fa_start = '1' and fa_done = '1') then
                        -- Ergebnis ist gültig (OUTPUT_STATE von float_add)
                        signal_writedata <= float_sum;
                        signal_write     <= '1';

                        -- ein Sample fertig
                        index      <= index + 1;

                        -- start zurücknehmen, damit float_add wieder in WAIT_STATE geht
                        fa_start   <= '0';
                    end if;

                when work.task.TASK_DONE =>
                    index            <= 0;
                    signal_write     <= '0';
                    signal_a_read    <= '0';
                    signal_b_read    <= '0';
                    signal_writedata <= (others => '0');
                    fa_start         <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;