------------------------------------------------------------------------
-- fft
--
-- calculation of FFT magnitude
--
-- Inputs:
-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
--
-- Outputs
-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
--
-----------------------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;
	 use work.float.all;













architecture rtl of fft is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

	--own signals:
	--signal input_re : float(31 downto 0);

	--use xxx.lib?; --componenteninstanziierung FFT IP-Core r22sdf
	--component foo is 
	--generic (...)
	--port(...);
	--end component;

		component fftmain is
			generic (

			-- input data width of real/img part
			input_data_width : integer := 32;

			-- output data width of real/img part
			output_data_width : integer := 32

			);
			port (
			clk : in std_logic;
			reset : in std_logic;

			di_en : in std_logic;
			di_re : in std_logic_vector(input_data_width-1 downto 0);
			di_im : in std_logic_vector(input_data_width-1 downto 0);
			
			do_en : in std_logic;
			do_re : in std_logic_vector(input_data_width-1 downto 0);
			do_im  : in std_logic_vector(input_data_width-1 downto 0)
			

			--task_start : in std_logic;
			--task_state : out work.task.State;

			--signal_read : out std_logic;
			--signal_readdata : in std_logic_vector( 31 downto 0 );

			--signal_write : out std_logic;
			--signal_writedata : out std_logic_vector( 31 downto 0 )
			);
		end component fftmain;


---State machine ----------------------------------
TYPE State_type IS (A, B, C, D);  -- Define the states
	SIGNAL State : State_Type;    -- Create a signal that uses 
							      -- the different states



begin

u_fft : fftmain
	port map (
		clock => clk,
		reset => fft_reset,

		di_en => fft_input_data_enable,
		di_re => diata_in_re,
		di_im => data_in_im,
		
		do_en => fft_output_valid,
		do_re => data_out_re,
		do_im => data_out_im
	);

u_fft_mag_calc : entity work.fft_magnitude_calc
	port map (
		clk => clk, 
		reset => reset,
		input_valid => fft_output_valid,
		input_re => data_out_re,
		input_im => data_out_im,
		output_valid => fft_mag_calc_valid,
		output_magnitude => fft_mag_calc_result
	);




    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
                signal_write <= '0';
            when work.task.TASK_RUNNING =>
                index <= index + 1;
                signal_write <= '1';
                signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                index <= 0;
                signal_write <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;