signal_processing_vorlage/hardware/system/data_channel.cmp.vhd

library ieee;
    use ieee.std_logic_1164.all;

entity data_channel is
    generic (
        DEPTH : positive := 1024
    );
    port (
        clk : in std_logic;
        reset : in std_logic;

        ctrl_address : in std_logic_vector( 3 downto 0 );
        ctrl_read : in std_logic;
        ctrl_readdata : out std_logic_vector( 31 downto 0 );
        ctrl_write : in std_logic;
        ctrl_writedata : in std_logic_vector( 31 downto 0 );

        hw_sink_write : in std_logic;
        hw_sink_writedata : in std_logic_vector( 31 downto 0 );

        hw_source_read : in std_logic;
        hw_source_readdata : out std_logic_vector( 31 downto 0 )
    );
end entity data_channel;