signal_processing_vorlage/hardware/system/data_sink_mux.vhd

library ieee;
    use ieee.std_logic_1164.all;

entity data_sink_mux is
    port (
        sel : in std_logic;

        sw_write : in std_logic;
        sw_writedata : in std_logic_vector( 31 downto 0 );

        hw_write : in std_logic;
        hw_writedata : in std_logic_vector( 31 downto 0 );

        write : out std_logic;
        writedata : out std_logic_vector( 31 downto 0 )
    );
end entity data_sink_mux;

architecture rtl of data_sink_mux is
begin
    write <= sw_write when sel = '0' else hw_write;

    writedata <= sw_writedata when sel = '0' else
        hw_writedata;

end architecture rtl;