signal_processing_vorlage/hardware/system/data_source_mux.vhd

library ieee;
    use ieee.std_logic_1164.all;

entity data_source_mux is
    port (
        sel : in std_logic;

        sw_read : in std_logic;
        sw_readdata : out std_logic_vector( 31 downto 0 );

        hw_read : in std_logic;
        hw_readdata : out std_logic_vector( 31 downto 0 );

        read : out std_logic;
        readdata : in std_logic_vector( 31 downto 0 )
    );
end entity data_source_mux;

architecture rtl of data_source_mux is
begin
    read <= sw_read when sel = '0' else hw_read;

    sw_readdata <= readdata;
    hw_readdata <= readdata;

end architecture rtl;