signal_processing_vorlage/hardware/system/reg32.vhd

library ieee;
    use ieee.std_logic_1164.all;

package reg32 is

    subtype Word is std_logic_vector( 31 downto 0 );

    type RegArray is array ( natural range <> ) of Word;

    type AccessType is (
        NONE,
        READ_ONLY,
        WRITE_ONLY,
        READ_WRITE
    );

    type AccessArray is array ( natural range <> ) of AccessType;

    function allows_read( access_type : AccessType )
        return boolean;

    function allows_write( access_type : AccessType )
        return boolean;

end package reg32;

package body reg32 is

    function allows_read( access_type : AccessType )
        return boolean is
    begin
        return access_type = READ_ONLY or access_type = READ_WRITE;
    end function allows_read;

    function allows_write( access_type : AccessType )
        return boolean is
    begin
        return access_type = WRITE_ONLY or access_type = READ_WRITE;
    end function allows_write;

end package body reg32;