signal_processing_vorlage/hardware/system/task.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;


package task is

    type State is (
        TASK_IDLE,
        TASK_RUNNING,
        TASK_DONE
    );

    function to_std_logic_vector( s : State; len : positive ) return std_logic_vector;

    constant STREAM_LEN : integer := 1024;

end package task;

package body task is

    function to_std_logic_vector( s : State; len : positive ) return std_logic_vector is
        constant MIN_LEN : positive := positive( ceil( log2( real( State'pos( State'right ) + 1 ) ) ) );
        variable vector : std_logic_vector( MIN_LEN - 1 downto 0 );
        variable output : std_logic_vector( len - 1 downto 0 );
    begin
        vector := std_logic_vector( to_unsigned( State'pos( s ), MIN_LEN ) );
        if ( len < MIN_LEN ) then
            output := ( others => 'U' );
        elsif ( len = MIN_LEN ) then
            output := vector;
        else
            output := ( others => '0' );
            output( vector'range ) := vector;
        end if;
        return output;
    end function to_std_logic_vector;

end package body task;