Studentenversion des ESY6/A Praktikums "signal_processing".
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task_add.vhd 1.8KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library work;
  5. use work.reg32.all;
  6. use work.task.all;
  7. entity task_add is
  8. port (
  9. clk : in std_logic;
  10. reset : in std_logic;
  11. address : in std_logic_vector( 3 downto 0 );
  12. read : in std_logic;
  13. readdata : out std_logic_vector( 31 downto 0 );
  14. write : in std_logic;
  15. writedata : in std_logic_vector( 31 downto 0 );
  16. signal_a_read : out std_logic;
  17. signal_a_readdata : in std_logic_vector( 31 downto 0 );
  18. signal_b_read : out std_logic;
  19. signal_b_readdata : in std_logic_vector( 31 downto 0 );
  20. signal_write : out std_logic;
  21. signal_writedata : out std_logic_vector( 31 downto 0 )
  22. );
  23. end entity task_add;
  24. architecture struct of task_add is
  25. signal task_start : std_logic;
  26. signal task_state : work.task.State := work.task.TASK_IDLE;
  27. signal task_config : work.reg32.RegArray( 0 to 2 );
  28. begin
  29. u_control: entity work.hardware_task_control
  30. port map (
  31. clk => clk,
  32. reset => reset,
  33. address => address,
  34. read => read,
  35. readdata => readdata,
  36. write => write,
  37. writedata => writedata,
  38. task_start => task_start,
  39. task_state => task_state,
  40. task_config => task_config
  41. );
  42. u_add: entity work.add
  43. port map (
  44. clk => clk,
  45. reset => reset,
  46. task_start => task_start,
  47. task_state => task_state,
  48. signal_a_read => signal_a_read,
  49. signal_a_readdata => signal_a_readdata,
  50. signal_b_read => signal_b_read,
  51. signal_b_readdata => signal_b_readdata,
  52. signal_write => signal_write,
  53. signal_writedata => signal_writedata
  54. );
  55. end architecture struct;