signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

	type AddState is(
		ADD_IDLE,
		ADD_READ,
		ADD_CALC,
		ADD_STORERESULT	
	);	
	signal curAddState : ADDState;
	signal nextAddState : ADDState; 
	
	signal a : std_logic_vector (31 downto 0);
	signal b : std_logic_vector (31 downto 0);
	signal startcore : std_logic;
	signal donecore : std_logic;
	signal sumcore : std_logic_vector (31 downto 0);
	

begin
	u_float_add : entity work.float_add
	port map( 
		clk => clk,
		reset => reset,
		start => startcore,
		done => donecore,
		A => a,
		B => b,
		sum =>	sumcore
	);

--Zuletzt haben wir den State transitions prozess angelegt. Ziegler nachfragen 
	add_state_transitions : process (all) is
	begin
		--if(reset ='1' and rising_edge(clk)) then
		nextAddState <= curAddState;
		case curAddState is
			when ADD_IDLE =>  
				if(current_task_state = work.task.TASK_RUNNING) then
					nextAddState <= ADD_CALC;
				end if;
			when ADD_READ =>
				nextAddState <= ADD_CALC;
			when ADD_CALC => Null;
				if(donecore = '1') then
				nextAddState <=ADD_STORERESULT;
				end if;
			when ADD_STORERESULT => 
				nextAddState <= ADD_READ;
			when others => 
				nextAddState <= curAddState;
		end case;

	end process add_state_transitions;
	
	add_process : process (clk,reset) is
	begin
		if(reset = '1') then
			curADDState <= ADD_CALC;
			index <= 0;
			signal_write <='0';
			signal_a_read <='0';
			signal_b_read <='0';
			startcore <= '0';
			signal_writedata <= (others => '0');
			b<=  (others => '0');
			a<=  (others => '0');
		elsif(rising_edge(clk)) then
			curAddState <= nextAddState;
			Case curAddState is 
				when ADD_IDLE =>
					NULL;
				when ADD_READ =>
					signal_write <= '0';
					signal_a_read <= '1';
					signal_b_read <= '1';
				when ADD_CALC =>
					signal_a_read <= '0';
					signal_b_read <= '0';
					a <= signal_a_readdata;
					b <= signal_b_readdata;
					startcore <= '1';
				when ADD_STORERESULT =>
					startcore <= '0';
					signal_writedata <= sumcore;
					signal_write <= '1';
					index <= index+1;
				
				when others =>Null;
			end case;
			if(current_task_state=work.task.TASK_DONE)then
				index <= 0;
				signal_write <= '0';
			end if;
		end if;
	end process add_process;


--
    task_state_transitions : process ( all ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN  ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
          --  index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
			NULL;
    --            index <= 0;
     --           signal_write <= '0';
            when work.task.TASK_RUNNING =>
			NULL;
   --             index <= index + 1;
   --             signal_write <= '1';
   --             signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
			NULL;      
	--          index <= 0;
    --            signal_write <= '0';
            end case;
--test
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;