33 lines
677 B
Tcl
33 lines
677 B
Tcl
# External clock clk_50 has a frequency of 50 MHz
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create_clock -period 20 [get_ports clk_input]
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derive_pll_clocks
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set clk_main u_pll_200|pll_200|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
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# Input delays for singals in 50 MHz domain
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set_input_delay \
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-clock { clk_input } \
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2 \
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[get_ports {reset_n}]
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# Input delays for singals in 200 MHz domain
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set_false_path \
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-from \
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[get_ports {key_start}]
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# Output delays for singals in 200 MHz domain
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set_false_path \
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-to \
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[get_ports { \
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leds[0] \
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leds[1] \
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leds[2] \
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leds[3] \
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leds[4] \
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leds[5] \
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leds[6] \
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leds[7] \
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}]
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