297 lines
8.7 KiB
VHDL
297 lines
8.7 KiB
VHDL
------------------------------------------------------------------------
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-- fft
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--
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-- calculation of FFT magnitude
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--
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-- Inputs:
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-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
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--
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-- Outputs
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-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
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--
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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use work.float.all;
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entity fft is
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generic (
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity fft;
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architecture rtl of fft is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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component fftmain is
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port(
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clock: in std_logic; -- Master Clock
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reset: in std_logic; -- Active High Asynchronous Reset
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di_en: in std_logic; -- Input Data Enable
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di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
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di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
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do_en: out std_logic; -- Output Data Enable
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do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
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do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
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);
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end component;
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--Initialisierung der weiteren Ablaufstruktur
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type FFTState is (
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FFTIdle,
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FFTRead,
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FFTWait,
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MAGRead,
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MAGStore
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);
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--Signale fuer die Zustandsmaschine
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signal current_fft_state : FFTState;
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signal next_fft_state : FFTState;
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--signal fifo_in : unsigned(31 downto 0);
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constant B : signed(7 downto 0) := "00000100";
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--signal C : unsigned(31 downto 0);
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--signal D : unsigned(31 downto 0);
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--signal E : unsigned(31 downto 0);
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--signal F : unsigned(31 downto 0);
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signal read_index : integer range 0 to work.task.STREAM_LEN +100;
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signal fft_index : integer range 0 to work.task.STREAM_LEN;
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signal result : std_logic_vector ( 31 downto 0 );
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signal input_valid : std_logic;
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signal input_re : std_logic_vector( 31 downto 0 ); -- in Fixpoint
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signal input_im : std_logic_vector( 31 downto 0 ); -- in Fixpoint
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signal output_valid : std_logic;
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signal output_magnitude : std_logic_vector( 31 downto 0 );
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signal cnt : integer range 0 to work.task.STREAM_LEN;
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signal di_en : std_logic; -- Input Data Enable
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signal di_re : std_logic_vector(31 downto 0); -- Input Data (Real)
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signal di_im : std_logic_vector(31 downto 0); -- Input Data (Imag)
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signal do_en : std_logic; -- Output Data Enable
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signal do_re : std_logic_vector(31 downto 0); -- Output Data (Real)
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signal do_im : std_logic_vector(31 downto 0); -- Output Data (Imag)
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begin
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--Port Zuweisung
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c_float_fft: entity work.fft_magnitude_calc
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PORT MAP (
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clk => clk,
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reset => reset,
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input_valid => input_valid,
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input_re => input_re, -- in Fixpoint
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input_im => input_im, -- in Fixpoint
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output_valid => output_valid,
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output_magnitude => output_magnitude
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);
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u_fft : fftmain
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port map (
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clock => clk,
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reset => reset,
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di_en => di_en,
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di_re => di_re,
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di_im => di_im,
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do_en => do_en,
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do_re => do_re,
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do_im => do_im
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);
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = (work.task.STREAM_LEN - 1) ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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----------------------------------------------------------------------
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--FFT Statemachine
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fft_state_transitions : process ( all ) is
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begin
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next_fft_state <= current_fft_state;
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case current_fft_state is
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when FFTIdle =>
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if ( current_task_state = work.task.TASK_RUNNING ) then -- Weiterschaltbedingung
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next_fft_state <= FFTRead;
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end if;
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when FFTRead =>
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if ( fft_index = work.task.STREAM_LEN ) then
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next_fft_state <= FFTWait;
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end if;
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when FFTWait =>
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if ( do_en = '1') then
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next_fft_state <= MAGRead;
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end if;
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when MAGRead =>
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if ( output_valid = '1' ) then -- Weiterschaltbedingung
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next_fft_state <= MAGStore;
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end if;
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when MAGStore =>
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if ( cnt = (work.task.STREAM_LEN - 1)) then
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next_fft_state <= FFTIdle;
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end if;
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end case;
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end process fft_state_transitions;
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----------------------------------------------------------------------
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sync : process ( clk, reset ) is
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variable fifo_in : signed(31 downto 0);
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variable fifo_in2 : signed(31 downto 0);
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variable mag_out : signed(31 downto 0);
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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read_index <= 0;
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fft_index <= 0;
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cnt <= 0;
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signal_write <= '0';
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signal_read <= '0';
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input_valid <= '0';
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fifo_in := (others => '0');
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fifo_in2 := (others => '0');
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mag_out := (others => '0');
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-- C <= (others => '0');
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-- D <= (others => '0');
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-- E <= (others => '0');
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--F <= (others => '0');
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input_re <= (others => '0');
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input_im <= (others => '0');
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signal_writedata <= (others => '0');
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di_en <= '0';
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di_re <= (others => '0');
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di_im <= (others => '0');
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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-- index <= index + 1; --Index wird hier hochgezählt, muss in FFT State gemacht werden
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-- signal_write <= '1';
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-- signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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----------------------------------------------------------------------
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--Output Statemachine
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current_fft_state <= next_fft_state;
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signal_write <= '0';
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signal_read <= '0';
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input_valid <= '0';
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di_en <= '0';
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case next_fft_state is
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when FFTIdle =>
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when FFTRead =>
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di_en <= '1';
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signal_read <= '1';
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--fifo_in <= signal_readdata(31 downto 0);
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if(signal_readdata(30 downto 23) /= "00000000") then
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fifo_in(31) := signal_readdata(31);
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fifo_in(30 downto 23) := signed(signal_readdata(30 downto 23)) - 4;
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fifo_in(22 downto 0) := signed(signal_readdata(22 downto 0));
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--fifo_in2 := (fifo_in(31) & (signed(fifo_in(30 downto 23)) - 4) & (signed(fifo_in(22 downto 0))));
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end if;
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di_re <= to_fixed(std_logic_vector(fifo_in));
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di_im <= (others => '0');
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fft_index <= fft_index +1;
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when FFTWait =>
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fft_index <= 0;
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when MAGRead =>
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--D <= do_im(31) & ( unsigned(do_im(30 downto 23)) - B ) & unsigned(do_im(22 downto 0));
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input_valid <= '1';
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input_re <= do_re;
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input_im <= do_im;
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read_index <= read_index + 1;
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when MAGStore =>
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--read
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if(read_index <= work.task.STREAM_LEN) then
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--A <= do_re(31) & ( unsigned(do_re(30 downto 23)) - B ) & unsigned(do_re(22 downto 0));
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--D <= do_im(31) & ( unsigned(do_im(30 downto 23)) - B ) & unsigned(do_im(22 downto 0));
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signal_read <= '1';
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input_valid <= '1';
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input_re <= do_re;
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input_im <= do_im;
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read_index <= read_index + 1;
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end if;
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--store
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signal_write <= '1';
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mag_out(31) := output_magnitude(31) ;
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mag_out(30 downto 23) := signed(output_magnitude(30 downto 23)) + 4;
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mag_out(22 downto 0) := signed(output_magnitude(22 downto 0));
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signal_writedata <= to_float(std_logic_vector(mag_out));
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index <= index + 1;
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cnt <= cnt + 1;
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end case;
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----------------------------------------------------------------------
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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