364 lines
14 KiB
VHDL
364 lines
14 KiB
VHDL
--! Use ieee library for std_logic types.
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library ieee;
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use ieee.std_logic_1164.all;
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--! Use the niosII library for all processor system components
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library niosII;
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--! Use the pll_200 library for the PLL 200 MHz clock generation
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library pll_main;
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entity signal_processing is
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port
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(
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clk_input : in std_logic;
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reset_n : in std_logic;
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--! Push button key_0 used to start a single execution of the signal
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--! processing.
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key_start : in std_logic;
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leds : out std_logic_vector( 7 downto 0 )
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);
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end entity signal_processing;
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architecture struct of signal_processing is
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--! input clock synchronous reset
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signal sync_reset : std_logic;
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--! main clock for the NiosII system
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signal clk_main : std_logic;
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--! main clock from PLL is locked and the system reset can be released.
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signal locked_main : std_logic;
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--! main clock synchronous reset
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signal sync_reset_main : std_logic;
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signal sync_reset_main_n : std_logic;
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signal sw_leds : std_logic_vector( 7 downto 0 );
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signal hw_leds : std_logic_vector( 7 downto 0 );
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signal hardware_task_0_address : std_logic_vector(3 downto 0);
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signal hardware_task_0_read : std_logic;
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signal hardware_task_0_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_0_write : std_logic;
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signal hardware_task_0_writedata : std_logic_vector(31 downto 0);
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signal hardware_task_1_address : std_logic_vector(3 downto 0);
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signal hardware_task_1_read : std_logic;
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signal hardware_task_1_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_1_write : std_logic;
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signal hardware_task_1_writedata : std_logic_vector(31 downto 0);
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signal hardware_task_2_address : std_logic_vector(3 downto 0);
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signal hardware_task_2_read : std_logic;
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signal hardware_task_2_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_2_write : std_logic;
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signal hardware_task_2_writedata : std_logic_vector(31 downto 0);
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signal hardware_task_3_address : std_logic_vector(3 downto 0);
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signal hardware_task_3_read : std_logic;
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signal hardware_task_3_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_3_write : std_logic;
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signal hardware_task_3_writedata : std_logic_vector(31 downto 0);
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signal hardware_task_4_address : std_logic_vector(3 downto 0);
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signal hardware_task_4_read : std_logic;
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signal hardware_task_4_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_4_write : std_logic;
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signal hardware_task_4_writedata : std_logic_vector(31 downto 0);
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signal hardware_task_5_address : std_logic_vector(3 downto 0);
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signal hardware_task_5_read : std_logic;
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signal hardware_task_5_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_5_write : std_logic;
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signal hardware_task_5_writedata : std_logic_vector(31 downto 0);
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signal hardware_task_6_address : std_logic_vector(3 downto 0);
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signal hardware_task_6_read : std_logic;
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signal hardware_task_6_readdata : std_logic_vector(31 downto 0);
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signal hardware_task_6_write : std_logic;
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signal hardware_task_6_writedata : std_logic_vector(31 downto 0);
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signal data_channel_0_hw_sink_write : std_logic;
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signal data_channel_0_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_0_hw_source_read : std_logic;
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signal data_channel_0_hw_source_readdata : std_logic_vector(31 downto 0);
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signal data_channel_1_hw_sink_write : std_logic;
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signal data_channel_1_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_1_hw_source_read : std_logic;
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signal data_channel_1_hw_source_readdata : std_logic_vector(31 downto 0);
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signal data_channel_2_hw_sink_write : std_logic;
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signal data_channel_2_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_2_hw_source_read : std_logic;
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signal data_channel_2_hw_source_readdata : std_logic_vector(31 downto 0);
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signal data_channel_3_hw_sink_write : std_logic;
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signal data_channel_3_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_3_hw_source_read : std_logic;
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signal data_channel_3_hw_source_readdata : std_logic_vector(31 downto 0);
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signal data_channel_4_hw_sink_write : std_logic;
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signal data_channel_4_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_4_hw_source_read : std_logic;
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signal data_channel_4_hw_source_readdata : std_logic_vector(31 downto 0);
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signal data_channel_5_hw_sink_write : std_logic;
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signal data_channel_5_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_5_hw_source_read : std_logic;
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signal data_channel_5_hw_source_readdata : std_logic_vector(31 downto 0);
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signal data_channel_6_hw_sink_write : std_logic;
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signal data_channel_6_hw_sink_writedata : std_logic_vector(31 downto 0);
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signal data_channel_6_hw_source_read : std_logic;
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signal data_channel_6_hw_source_readdata : std_logic_vector(31 downto 0);
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begin
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-- Synchronize the external reset to the external clock domain
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u_sync_rst_50: entity work.sync_rst
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port map
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(
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clk => clk_input,
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reset => not reset_n,
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rst_sync => sync_reset
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);
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-- PLL for the main system clock
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u_pll_main: entity pll_main.pll_main
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port map
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(
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refclk => clk_input, -- in std_logic
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rst => sync_reset, -- in std_logic
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outclk_0 => clk_main, -- out std_logic
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locked => locked_main -- out std_logic
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);
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-- Synchronize the main reset to the main clock domain
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u_sync_rst_main: entity work.sync_rst
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port map
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(
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clk => clk_main,
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reset => not locked_main and sync_reset,
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rst_sync => sync_reset_main
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);
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sync_reset_main_n <= not sync_reset_main;
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-- NiosII system
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u_niosII : entity niosii.niosII
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port map
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(
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clk_clk => clk_main,
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reset_reset_n => sync_reset_main_n,
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key_start_export => key_start,
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leds_export => sw_leds,
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data_channel_0_hw_sink_write => data_channel_0_hw_sink_write,
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data_channel_0_hw_sink_writedata => data_channel_0_hw_sink_writedata,
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data_channel_0_hw_source_read => data_channel_0_hw_source_read,
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data_channel_0_hw_source_readdata => data_channel_0_hw_source_readdata,
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data_channel_1_hw_sink_write => data_channel_1_hw_sink_write,
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data_channel_1_hw_sink_writedata => data_channel_1_hw_sink_writedata,
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data_channel_1_hw_source_read => data_channel_1_hw_source_read,
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data_channel_1_hw_source_readdata => data_channel_1_hw_source_readdata,
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data_channel_2_hw_sink_write => data_channel_2_hw_sink_write,
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data_channel_2_hw_sink_writedata => data_channel_2_hw_sink_writedata,
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data_channel_2_hw_source_read => data_channel_2_hw_source_read,
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data_channel_2_hw_source_readdata => data_channel_2_hw_source_readdata,
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data_channel_3_hw_sink_write => data_channel_3_hw_sink_write,
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data_channel_3_hw_sink_writedata => data_channel_3_hw_sink_writedata,
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data_channel_3_hw_source_read => data_channel_3_hw_source_read,
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data_channel_3_hw_source_readdata => data_channel_3_hw_source_readdata,
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data_channel_4_hw_sink_write => data_channel_4_hw_sink_write,
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data_channel_4_hw_sink_writedata => data_channel_4_hw_sink_writedata,
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data_channel_4_hw_source_read => data_channel_4_hw_source_read,
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data_channel_4_hw_source_readdata => data_channel_4_hw_source_readdata,
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data_channel_5_hw_sink_write => data_channel_5_hw_sink_write,
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data_channel_5_hw_sink_writedata => data_channel_5_hw_sink_writedata,
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data_channel_5_hw_source_read => data_channel_5_hw_source_read,
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data_channel_5_hw_source_readdata => data_channel_5_hw_source_readdata,
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data_channel_6_hw_sink_write => data_channel_6_hw_sink_write,
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data_channel_6_hw_sink_writedata => data_channel_6_hw_sink_writedata,
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data_channel_6_hw_source_read => data_channel_6_hw_source_read,
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data_channel_6_hw_source_readdata => data_channel_6_hw_source_readdata,
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hardware_task_0_task_address => hardware_task_0_address,
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hardware_task_0_task_read => hardware_task_0_read,
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hardware_task_0_task_readdata => hardware_task_0_readdata,
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hardware_task_0_task_write => hardware_task_0_write,
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hardware_task_0_task_writedata => hardware_task_0_writedata,
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hardware_task_1_task_address => hardware_task_1_address,
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hardware_task_1_task_read => hardware_task_1_read,
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hardware_task_1_task_readdata => hardware_task_1_readdata,
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hardware_task_1_task_write => hardware_task_1_write,
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hardware_task_1_task_writedata => hardware_task_1_writedata,
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hardware_task_2_task_address => hardware_task_2_address,
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hardware_task_2_task_read => hardware_task_2_read,
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hardware_task_2_task_readdata => hardware_task_2_readdata,
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hardware_task_2_task_write => hardware_task_2_write,
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hardware_task_2_task_writedata => hardware_task_2_writedata,
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hardware_task_3_task_address => hardware_task_3_address,
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hardware_task_3_task_read => hardware_task_3_read,
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hardware_task_3_task_readdata => hardware_task_3_readdata,
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hardware_task_3_task_write => hardware_task_3_write,
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hardware_task_3_task_writedata => hardware_task_3_writedata,
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hardware_task_4_task_address => hardware_task_4_address,
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hardware_task_4_task_read => hardware_task_4_read,
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hardware_task_4_task_readdata => hardware_task_4_readdata,
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hardware_task_4_task_write => hardware_task_4_write,
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hardware_task_4_task_writedata => hardware_task_4_writedata,
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hardware_task_5_task_address => hardware_task_5_address,
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hardware_task_5_task_read => hardware_task_5_read,
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hardware_task_5_task_readdata => hardware_task_5_readdata,
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hardware_task_5_task_write => hardware_task_5_write,
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hardware_task_5_task_writedata => hardware_task_5_writedata,
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hardware_task_6_task_address => hardware_task_6_address,
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hardware_task_6_task_read => hardware_task_6_read,
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hardware_task_6_task_readdata => hardware_task_6_readdata,
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hardware_task_6_task_write => hardware_task_6_write,
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hardware_task_6_task_writedata => hardware_task_6_writedata
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);
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u_task_sine: entity work.task_sine
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_0_address,
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read => hardware_task_0_read,
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readdata => hardware_task_0_readdata,
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write => hardware_task_0_write,
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writedata => hardware_task_0_writedata,
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signal_write => data_channel_0_hw_sink_write ,
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signal_writedata => data_channel_0_hw_sink_writedata
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);
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u_task_cosine: entity work.task_sine
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_1_address,
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read => hardware_task_1_read,
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readdata => hardware_task_1_readdata,
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write => hardware_task_1_write,
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writedata => hardware_task_1_writedata,
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signal_write => data_channel_1_hw_sink_write ,
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signal_writedata => data_channel_1_hw_sink_writedata
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);
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u_task_rand: entity work.task_rand
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_2_address,
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read => hardware_task_2_read,
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readdata => hardware_task_2_readdata,
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write => hardware_task_2_write,
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writedata => hardware_task_2_writedata,
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signal_write => data_channel_2_hw_sink_write ,
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signal_writedata => data_channel_2_hw_sink_writedata
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);
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u_task_add_sine_cosine: entity work.task_add
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_3_address,
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read => hardware_task_3_read,
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readdata => hardware_task_3_readdata,
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write => hardware_task_3_write,
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writedata => hardware_task_3_writedata,
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signal_a_read => data_channel_0_hw_source_read,
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signal_a_readdata => data_channel_0_hw_source_readdata,
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signal_b_read => data_channel_1_hw_source_read,
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signal_b_readdata => data_channel_1_hw_source_readdata,
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signal_write => data_channel_3_hw_sink_write ,
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signal_writedata => data_channel_3_hw_sink_writedata
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);
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u_task_add_rand: entity work.task_add
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_4_address,
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read => hardware_task_4_read,
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readdata => hardware_task_4_readdata,
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write => hardware_task_4_write,
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writedata => hardware_task_4_writedata,
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signal_a_read => data_channel_2_hw_source_read,
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signal_a_readdata => data_channel_2_hw_source_readdata,
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signal_b_read => data_channel_3_hw_source_read,
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signal_b_readdata => data_channel_3_hw_source_readdata,
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signal_write => data_channel_4_hw_sink_write ,
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signal_writedata => data_channel_4_hw_sink_writedata
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);
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u_task_fft: entity work.task_fft
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_5_address,
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read => hardware_task_5_read,
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readdata => hardware_task_5_readdata,
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write => hardware_task_5_write,
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writedata => hardware_task_5_writedata,
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signal_read => data_channel_4_hw_source_read,
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signal_readdata => data_channel_4_hw_source_readdata,
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signal_write => data_channel_5_hw_sink_write ,
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signal_writedata => data_channel_5_hw_sink_writedata
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);
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u_task_crc: entity work.task_crc
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port map (
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clk => clk_main,
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reset => sync_reset_main,
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address => hardware_task_6_address,
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read => hardware_task_6_read,
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readdata => hardware_task_6_readdata,
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write => hardware_task_6_write,
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writedata => hardware_task_6_writedata,
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signal_read => data_channel_5_hw_source_read,
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signal_readdata => data_channel_5_hw_source_readdata,
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signal_write => data_channel_6_hw_sink_write ,
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signal_writedata => data_channel_6_hw_sink_writedata
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);
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hw_leds <= ( 0 => reset_n, 1 => sync_reset, 2 => locked_main, 3 => sync_reset_main, others => '0' );
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leds <= sw_leds or hw_leds;
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end architecture struct;
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