36 lines
1.0 KiB
Verilog
36 lines
1.0 KiB
Verilog
//----------------------------------------------------------------------
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// Multiply: Complex Multiplier
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//----------------------------------------------------------------------
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module Multiply #(
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parameter WIDTH = 16
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)(
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input signed [WIDTH-1:0] a_re,
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input signed [WIDTH-1:0] a_im,
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input signed [WIDTH-1:0] b_re,
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input signed [WIDTH-1:0] b_im,
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output signed [WIDTH-1:0] m_re,
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output signed [WIDTH-1:0] m_im
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);
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wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi;
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wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi;
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// Signed Multiplication
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assign arbr = a_re * b_re;
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assign arbi = a_re * b_im;
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assign aibr = a_im * b_re;
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assign aibi = a_im * b_im;
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// Scaling
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assign sc_arbr = arbr >>> (WIDTH-1);
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assign sc_arbi = arbi >>> (WIDTH-1);
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assign sc_aibr = aibr >>> (WIDTH-1);
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assign sc_aibi = aibi >>> (WIDTH-1);
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// Sub/Add
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// These sub/add may overflow if unnormalized data is input.
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assign m_re = sc_arbr - sc_aibi;
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assign m_im = sc_arbi + sc_aibr;
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endmodule
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