26 lines
685 B
VHDL
26 lines
685 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity data_channel is
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generic (
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DEPTH : positive := 1024
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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ctrl_address : in std_logic_vector( 3 downto 0 );
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ctrl_read : in std_logic;
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ctrl_readdata : out std_logic_vector( 31 downto 0 );
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ctrl_write : in std_logic;
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ctrl_writedata : in std_logic_vector( 31 downto 0 );
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hw_sink_write : in std_logic;
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hw_sink_writedata : in std_logic_vector( 31 downto 0 );
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hw_source_read : in std_logic;
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hw_source_readdata : out std_logic_vector( 31 downto 0 )
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);
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end entity data_channel;
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