123 lines
3.2 KiB
VHDL
123 lines
3.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity data_channel is
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generic (
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DEPTH : positive := 1024
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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ctrl_address : in std_logic_vector( 3 downto 0 );
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ctrl_read : in std_logic;
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ctrl_readdata : out std_logic_vector( 31 downto 0 );
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ctrl_write : in std_logic;
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ctrl_writedata : in std_logic_vector( 31 downto 0 );
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hw_sink_write : in std_logic;
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hw_sink_writedata : in std_logic_vector( 31 downto 0 );
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hw_source_read : in std_logic;
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hw_source_readdata : out std_logic_vector( 31 downto 0 )
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);
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end entity data_channel;
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architecture struct of data_channel is
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signal sink_config : std_logic;
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signal source_config : std_logic;
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signal clear : std_logic;
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signal empty : std_logic;
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signal full : std_logic;
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signal level : std_logic_vector( 9 downto 0 );
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signal ctrl_sink_write : std_logic;
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signal ctrl_sink_writedata : std_logic_vector( 31 downto 0 );
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signal ctrl_source_read : std_logic;
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signal ctrl_source_readdata : std_logic_vector( 31 downto 0 );
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signal sink_write : std_logic;
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signal sink_writedata : std_logic_vector( 31 downto 0 );
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signal source_read : std_logic;
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signal source_readdata : std_logic_vector( 31 downto 0 );
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begin
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u_control : entity work.data_channel_control
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port map (
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clk => clk,
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reset => reset,
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address => ctrl_address,
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read => ctrl_read,
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readdata => ctrl_readdata,
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write => ctrl_write,
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writedata => ctrl_writedata,
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sink_config => sink_config,
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source_config => source_config,
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clear => clear,
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empty => empty,
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full => full,
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level => level,
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sink_write => ctrl_sink_write,
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sink_writedata => ctrl_sink_writedata,
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source_read => ctrl_source_read,
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source_readdata => ctrl_source_readdata
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);
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u_data_sink_mux : entity work.data_sink_mux
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port map (
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sel => sink_config,
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sw_write => ctrl_sink_write,
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sw_writedata => ctrl_sink_writedata,
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hw_write => hw_sink_write,
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hw_writedata => hw_sink_writedata,
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write => sink_write,
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writedata => sink_writedata
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);
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u_fifo : entity work.fifo
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generic map (
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DEPTH => DEPTH
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)
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port map (
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aclr => reset,
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clock => clk,
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sclr => clear,
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data => sink_writedata,
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rdreq => source_read,
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wrreq => sink_write,
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empty => empty,
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full => full,
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q => source_readdata,
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usedw => level
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);
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u_data_source_mux : entity work.data_source_mux
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port map (
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sel => source_config,
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sw_read => ctrl_source_read,
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sw_readdata => ctrl_source_readdata,
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hw_read => hw_source_read,
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hw_readdata => hw_source_readdata,
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read => source_read,
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readdata => source_readdata
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);
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end architecture;
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