84 lines
2.5 KiB
VHDL
84 lines
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library work;
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use work.cordic_pkg.all;
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entity fixed_sine is
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generic (
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SIZE : positive; -- Width of parameters
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ITERATIONS : positive; -- Number of CORDIC iterations
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FRAC_BITS : positive; -- Total fractional bits
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MAGNITUDE : real := 1.0;
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RESET_ACTIVE_LEVEL : std_ulogic := '1'
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);
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port (
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clock : in std_ulogic;
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reset : in std_ulogic;
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data_valid : in std_ulogic; --# load new input data
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busy : out std_ulogic; --# generating new result
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result_valid : out std_ulogic; --# flag when result is valid
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angle : in signed(size-1 downto 0); -- angle in brads (2**size brads = 2*pi radians)
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sine : out signed(size-1 downto 0)
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);
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end entity fixed_sine;
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architecture rtl of fixed_sine is
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signal xa, ya, za, x_result, y_result : signed(Angle'range);
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signal rv_loc : std_ulogic;
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begin
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adj: process(clock, reset) is
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constant Y : signed(Angle'range) := (others => '0');
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constant X : signed(Angle'range) := --to_signed(1, Angle'length);
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to_signed(integer(MAGNITUDE/cordic_gain(ITERATIONS) * 2.0 ** FRAC_BITS), Angle'length);
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begin
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if reset = RESET_ACTIVE_LEVEL then
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xa <= (others => '0');
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ya <= (others => '0');
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za <= (others => '0');
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elsif rising_edge(clock) then
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adjust_angle(X, Y, Angle, xa, ya, za);
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end if;
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end process;
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c: entity work.cordic
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generic map (
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SIZE => SIZE,
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ITERATIONS => ITERATIONS,
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RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
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)
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port map (
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clock => clock,
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reset => reset,
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data_valid => data_valid,
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result_valid => rv_loc,
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busy => busy,
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Mode => cordic_rotate,
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X => xa,
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Y => ya,
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Z => za,
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X_result => x_result,
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Y_result => y_result,
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Z_result => open
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);
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reg: process(clock, reset) is
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begin
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if reset = RESET_ACTIVE_LEVEL then
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sine <= (others => '0');
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result_valid <= '0';
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elsif rising_edge(clock) then
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result_valid <= rv_loc;
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if rv_loc = '1' then -- Capture result
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sine <= y_result;
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end if;
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end if;
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end process;
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end architecture;
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