50 lines
1.2 KiB
VHDL
50 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library work;
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use work.cordic_pkg.all;
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use work.float.all;
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entity float_sine is
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generic (
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ITERATIONS : positive -- Number of CORDIC iterations
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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data_valid : in std_logic; --# load new input data
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busy : out std_logic; --# generating new result
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result_valid : out std_logic; --# flag when result is valid
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angle : in signed(31 downto 0); -- angle in brads (2**size brads = 2*pi radians)
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sine : out signed(31 downto 0)
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);
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end entity float_sine;
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architecture rtl of float_sine is
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signal fixed : signed( 31 downto 0 );
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begin
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u_fixed_sine : entity work.fixed_sine
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generic map (
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SIZE => 32,
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ITERATIONS => 8,
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FRAC_BITS => 31
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)
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port map (
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clock => clk,
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reset => reset,
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data_valid => data_valid,
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busy => busy,
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result_valid => result_valid,
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angle => angle,
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sine => fixed
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);
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sine <= signed( to_float( std_logic_vector( fixed ) ) );
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end architecture;
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