14 lines
335 B
VHDL
14 lines
335 B
VHDL
entity timer is
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port (
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clk : in std_logic;
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reset : in std_logic;
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address : in std_logic_vector( 3 downto 0 );
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read : in std_logic;
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readdata : out std_logic_vector( 31 downto 0 );
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write : in std_logic;
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writedata : in std_logic_vector( 31 downto 0 )
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);
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end entity timer;
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