43 lines
954 B
VHDL
43 lines
954 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package reg32 is
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subtype Word is std_logic_vector( 31 downto 0 );
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type RegArray is array ( natural range <> ) of Word;
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type AccessType is (
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NONE,
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READ_ONLY,
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WRITE_ONLY,
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READ_WRITE
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);
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type AccessArray is array ( natural range <> ) of AccessType;
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function allows_read( access_type : AccessType )
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return boolean;
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function allows_write( access_type : AccessType )
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return boolean;
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end package reg32;
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package body reg32 is
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function allows_read( access_type : AccessType )
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return boolean is
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begin
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return access_type = READ_ONLY or access_type = READ_WRITE;
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end function allows_read;
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function allows_write( access_type : AccessType )
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return boolean is
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begin
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return access_type = WRITE_ONLY or access_type = READ_WRITE;
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end function allows_write;
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end package body reg32;
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