44 lines
764 B
VHDL
44 lines
764 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity sync_rst is
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generic
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(
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WIDTH : positive range 2 to 5 := 3
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);
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port
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(
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clk : in std_logic;
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reset : in std_logic;
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rst_sync : out std_logic
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);
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end entity sync_rst;
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architecture rtl of sync_rst is
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--! Synchronization FFs
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signal sync : std_logic_vector( WIDTH - 1 downto 0 );
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begin
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p_sync: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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sync <= ( others => '1' );
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elsif ( rising_edge( clk ) ) then
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sync( 0 ) <= '0';
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sync( WIDTH - 1 downto 1 ) <= sync( WIDTH - 2 downto 0 );
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end if;
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end process p_sync;
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rst_sync <= sync( WIDTH - 1 );
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end architecture rtl;
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